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Searched refs:pup (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_pbs.c48 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; in ddr3_tip_pbs() local
86 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
87 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
90 min_adll_per_pup[if_id][pup] = in ddr3_tip_pbs()
92 pup_state[if_id][pup] = 0x3; in ddr3_tip_pbs()
93 adll_shift_lock[if_id][pup] = 1; in ddr3_tip_pbs()
94 max_adll_per_pup[if_id][pup] = 0x0; in ddr3_tip_pbs()
99 for (pup = 0; pup < octets_per_if_num; pup++) { in ddr3_tip_pbs()
100 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_pbs()
106 bit + pup * BUS_WIDTH_IN_BITS], in ddr3_tip_pbs()
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H A Dddr3_training_hw_algo.c162 u32 pup = 0, if_id = 0, num_pup = 0, rep = 0; in ddr3_tip_vref() local
184 for (pup = 0; in ddr3_tip_vref()
185 pup < octets_per_if_num; pup++) { in ddr3_tip_vref()
186 current_vref[pup][if_id] = 0; in ddr3_tip_vref()
187 last_vref[pup][if_id] = 0; in ddr3_tip_vref()
188 lim_vref[pup][if_id] = 0; in ddr3_tip_vref()
189 current_valid_window[pup][if_id] = 0; in ddr3_tip_vref()
190 last_valid_window[pup][if_id] = 0; in ddr3_tip_vref()
191 if (vref_window_size[if_id][pup] > in ddr3_tip_vref()
193 pup_st[pup][if_id] = VREF_CONVERGE; in ddr3_tip_vref()
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H A Dddr3_debug.c946 u32 pup = 0, start_pup = 0, end_pup = 0; in ddr3_tip_run_sweep_test() local
980 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
981 ctrl_sweepres[adll][if_id][pup] = in ddr3_tip_run_sweep_test()
997 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1007 pup_access, pup, DDR_PHY_DATA, in ddr3_tip_run_sweep_test()
1018 ctrl_sweepres[adll][if_id][pup] in ddr3_tip_run_sweep_test()
1027 pup, in ddr3_tip_run_sweep_test()
1033 + pup])); in ddr3_tip_run_sweep_test()
1045 for (pup = start_pup; pup <= end_pup; pup++) { in ddr3_tip_run_sweep_test()
1046 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, pup); in ddr3_tip_run_sweep_test()
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dqs.c68 int ddr3_check_window_limits(u32 pup, int high_limit, int low_limit, int is_tx,
297 u32 victim_dq, pup, tmp; in ddr3_find_adll_limits() local
326 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
327 centralization_low_limit[pup] = ADLL_MIN; in ddr3_find_adll_limits()
328 centralization_high_limit[pup] = ADLL_MAX; in ddr3_find_adll_limits()
342 for (pup = 0; pup < max_pup; pup++) in ddr3_find_adll_limits()
343 pup_mask |= (1 << pup); in ddr3_find_adll_limits()
345 for (pup = 0; pup < max_pup; pup++) { in ddr3_find_adll_limits()
347 analog_pbs_sum[pup][dq][0] = adll_start_val; in ddr3_find_adll_limits()
348 analog_pbs_sum[pup][dq][1] = adll_end_val; in ddr3_find_adll_limits()
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H A Dddr3_pbs.c66 static void ddr3_pbs_write_pup_dqs_reg(u32 cs, u32 pup, u32 dqs_delay);
96 u32 pup, dq, pups, cur_max_pup, valid_pup, reg; in ddr3_pbs_tx() local
124 for (pup = 0; pup < pups; pup++) { in ddr3_pbs_tx()
126 skew_sum_array[pup][dq] = 0; in ddr3_pbs_tx()
172 for (pup = 0; pup < cur_max_pup; pup++) { in ddr3_pbs_tx()
175 pup + ecc * in ddr3_pbs_tx()
203 pbs_dq_mapping[pup * in ddr3_pbs_tx()
244 for (pup = 0; pup < cur_max_pup; pup++) { in ddr3_pbs_tx()
250 DEBUG_PBS_D((pup + (ecc * ECC_PUP)), 1); in ddr3_pbs_tx()
265 [((pup) * DQ_NUM) + in ddr3_pbs_tx()
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H A Dddr3_write_leveling.c49 static void ddr3_write_ctrl_pup_reg(int bc_acc, u32 pup, u32 reg_addr,
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
108 for (pup = 0; in ddr3_write_leveling_hw()
109 pup < dram_info->num_of_total_pups; in ddr3_write_leveling_hw()
110 pup++) { in ddr3_write_leveling_hw()
111 if (pup == dram_info->num_of_std_pups in ddr3_write_leveling_hw()
113 pup = ECC_PUP; in ddr3_write_leveling_hw()
116 pup); in ddr3_write_leveling_hw()
121 dram_info->wl_val[cs][pup][P] = phase; in ddr3_write_leveling_hw()
122 dram_info->wl_val[cs][pup][D] = delay; in ddr3_write_leveling_hw()
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H A Dddr3_read_leveling.c91 u32 delay, phase, pup, cs; in ddr3_read_leveling_hw() local
99 for (pup = 0; in ddr3_read_leveling_hw()
100 pup < dram_info->num_of_total_pups; in ddr3_read_leveling_hw()
101 pup++) { in ddr3_read_leveling_hw()
102 if (pup == dram_info->num_of_std_pups in ddr3_read_leveling_hw()
104 pup = ECC_PUP; in ddr3_read_leveling_hw()
107 pup); in ddr3_read_leveling_hw()
111 dram_info->rl_val[cs][pup][P] = phase; in ddr3_read_leveling_hw()
116 dram_info->rl_val[cs][pup][D] = delay; in ddr3_read_leveling_hw()
117 dram_info->rl_val[cs][pup][S] = in ddr3_read_leveling_hw()
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H A Dddr3_sdram.c91 static void compare_pattern_v1(u32 uj, u32 *pup, u32 *pattern, in compare_pattern_v1() argument
100 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0xFF)) { in compare_pattern_v1()
107 *pup |= (1 << (uk + (PUP_NUM_32BIT * in compare_pattern_v1()
129 static void compare_pattern_v2(u32 uj, u32 *pup, u32 *pattern) in compare_pattern_v2() argument
136 if (((sdram_data[uj]) != (pattern[uj])) && (*pup != 0x3)) { in compare_pattern_v2()
143 *pup |= (1 << (uk % PUP_NUM_16BIT)); in compare_pattern_v2()
225 u32 pup = 0; in ddr3_sdram_dm_compare() local
239 compare_pattern_v1(uj, &pup, pattern, pup_groups, 0); in ddr3_sdram_dm_compare()
258 *new_locked_pup |= pup; in ddr3_sdram_dm_compare()
291 u32 ui, dq, pup; in ddr3_sdram_pbs_compare() local
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H A Dddr3_hw_training.c547 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay) in ddr3_write_pup_reg() argument
551 if (pup == PUP_BC) in ddr3_write_pup_reg()
554 reg |= (pup << REG_PHY_PUP_OFFS); in ddr3_write_pup_reg()
575 if (pup == PUP_BC) in ddr3_write_pup_reg()
578 reg |= (pup << REG_PHY_PUP_OFFS); in ddr3_write_pup_reg()
597 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup) in ddr3_read_pup_reg() argument
601 reg = (pup << REG_PHY_PUP_OFFS) | in ddr3_read_pup_reg()
697 u32 val, pup, tmp_cs, cs, i, dq; in ddr3_save_training() local
718 for (pup = 0; pup < dram_info->num_of_total_pups; in ddr3_save_training()
719 pup++) { in ddr3_save_training()
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H A Dddr3_hw_training.h326 void ddr3_write_pup_reg(u32 mode, u32 cs, u32 pup, u32 phase, u32 delay);
327 u32 ddr3_read_pup_reg(u32 mode, u32 cs, u32 pup);
/openbmc/linux/arch/arm/mach-s3c/
H A Dgpio-samsung.c45 u32 pup; in samsung_gpio_setpull_updown() local
47 pup = __raw_readl(reg); in samsung_gpio_setpull_updown()
48 pup &= ~(3 << shift); in samsung_gpio_setpull_updown()
49 pup |= pull << shift; in samsung_gpio_setpull_updown()
50 __raw_writel(pup, reg); in samsung_gpio_setpull_updown()
60 u32 pup = __raw_readl(reg); in samsung_gpio_getpull_updown() local
62 pup >>= shift; in samsung_gpio_getpull_updown()
63 pup &= 0x3; in samsung_gpio_getpull_updown()
65 return (__force samsung_gpio_pull_t)pup; in samsung_gpio_getpull_updown()
/openbmc/linux/arch/arm/mach-imx/
H A Dsrc.c102 u32 val, pup; in imx_gpcv2_set_core1_pdn_pup_by_software() local
110 ret = readl_relaxed_poll_timeout_atomic(gpc_base + reg, pup, in imx_gpcv2_set_core1_pdn_pup_by_software()
111 !(pup & BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7), in imx_gpcv2_set_core1_pdn_pup_by_software()
/openbmc/linux/drivers/pmdomain/imx/
H A Dgpcv2.c272 u16 pup; member
352 regmap_update_bits(domain->regmap, domain->regs->pup, in imx_pgc_power_up()
359 domain->regs->pup, reg_val, in imx_pgc_power_up()
549 .pup = GPC_PU_PGC_SW_PUP_REQ,
1209 .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
/openbmc/linux/include/linux/
H A Dhp_sdc.h278 hp_sdc_irqhook *timer, *reg, *hil, *pup, *cooked; member
/openbmc/linux/drivers/input/serio/
H A Dhp_sdc.c258 if (hp_sdc.pup != NULL) in hp_sdc_isr()
259 hp_sdc.pup(irq, dev_id, status, data); in hp_sdc_isr()
842 hp_sdc.pup = NULL; in hp_sdc_init()
/openbmc/openbmc/poky/meta/recipes-devtools/rust/files/
H A Dzlib-off64_t.patch29 …53961695bd432035c58347386a420d3388232376ebabe211","src/zlib/amiga/Makefile.pup":"a65cb3cd40b1b8ec7…
31 …53961695bd432035c58347386a420d3388232376ebabe211","src/zlib/amiga/Makefile.pup":"a65cb3cd40b1b8ec7…
/openbmc/linux/Documentation/admin-guide/
H A Ddevices.txt650 38 = /dev/inet/pup
663 /dev/pup -> /dev/inet/pup