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Searched refs:port_mmio (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/ata/
H A Dlibahci.c295 void __iomem *port_mmio = ahci_port_base(ap); in ahci_show_port_cmd() local
299 ret = sprintf(buf, "%x\n", readl(port_mmio + PORT_CMD)); in ahci_show_port_cmd()
449 void __iomem *port_mmio; in ahci_save_initial_config() local
588 port_mmio = __ahci_port_base(hpriv, i); in ahci_save_initial_config()
590 readl(port_mmio + PORT_CMD) & PORT_CMD_CAP; in ahci_save_initial_config()
624 void __iomem *port_mmio; in ahci_restore_initial_config() local
634 port_mmio = __ahci_port_base(hpriv, i); in ahci_restore_initial_config()
635 writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD); in ahci_restore_initial_config()
658 void __iomem *port_mmio = ahci_port_base(link->ap); in ahci_scr_read() local
662 *val = readl(port_mmio + offset); in ahci_scr_read()
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H A Dahci_xgene.c141 void __iomem *port_mmio = ahci_port_base(ap); in xgene_ahci_restart_engine() local
150 if (xgene_ahci_poll_reg_val(ap, port_mmio + in xgene_ahci_restart_engine()
162 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
163 writel(fbs | PORT_FBS_EN, port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
164 fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_restart_engine()
195 void __iomem *port_mmio = ahci_port_base(ap); in xgene_ahci_qc_issue() local
202 port_fbs = readl(port_mmio + PORT_FBS); in xgene_ahci_qc_issue()
205 writel(port_fbs, port_mmio + PORT_FBS); in xgene_ahci_qc_issue()
358 void __iomem *port_mmio = ahci_port_base(ap); in xgene_ahci_do_hardreset() local
372 val = readl(port_mmio + PORT_SCR_ERR); in xgene_ahci_do_hardreset()
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H A Dsata_mv.c637 static int mv_stop_edma_engine(void __iomem *port_mmio);
917 void __iomem *port_mmio = mv_ap_base(ap); in mv_save_cached_regs() local
920 pp->cached.fiscfg = readl(port_mmio + FISCFG); in mv_save_cached_regs()
921 pp->cached.ltmode = readl(port_mmio + LTMODE); in mv_save_cached_regs()
922 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); in mv_save_cached_regs()
923 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); in mv_save_cached_regs()
961 static void mv_set_edma_ptrs(void __iomem *port_mmio, in mv_set_edma_ptrs() argument
974 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); in mv_set_edma_ptrs()
976 port_mmio + EDMA_REQ_Q_IN_PTR); in mv_set_edma_ptrs()
977 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); in mv_set_edma_ptrs()
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H A Dahci_mvebu.c121 void __iomem *port_mmio = ahci_port_base(ap); in ahci_mvebu_stop_engine() local
124 tmp = readl(port_mmio + PORT_CMD); in ahci_mvebu_stop_engine()
131 port_fbs = readl(port_mmio + PORT_FBS); in ahci_mvebu_stop_engine()
135 writel(tmp, port_mmio + PORT_CMD); in ahci_mvebu_stop_engine()
142 writel(port_fbs, port_mmio + PORT_FBS); in ahci_mvebu_stop_engine()
145 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, in ahci_mvebu_stop_engine()
H A Dahci_qoriq.c92 void __iomem *port_mmio = ahci_port_base(link->ap); in ahci_qoriq_hardreset() local
118 px_cmd = readl(port_mmio + PORT_CMD); in ahci_qoriq_hardreset()
119 px_is = readl(port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset()
132 px_val = readl(port_mmio + PORT_CMD); in ahci_qoriq_hardreset()
134 writel(px_cmd, port_mmio + PORT_CMD); in ahci_qoriq_hardreset()
136 px_val = readl(port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset()
138 writel(px_is, port_mmio + PORT_IRQ_STAT); in ahci_qoriq_hardreset()
H A Dahci_dwc.c264 void __iomem *port_mmio; in ahci_dwc_init_dmacr() local
283 port_mmio = __ahci_port_base(hpriv, port); in ahci_dwc_init_dmacr()
284 dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr()
298 writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_init_dmacr()
344 void __iomem *port_mmio; in ahci_dwc_reinit_host() local
360 port_mmio = __ahci_port_base(hpriv, i); in ahci_dwc_reinit_host()
361 writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR); in ahci_dwc_reinit_host()
H A Dpata_pdc2027x.c174 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset) in port_mmio() function
188 return port_mmio(ap, offset) + adj; in dev_mmio()
206 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL)); in pdc2027x_cable_detect()
224 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02; in pdc2027x_port_enabled()
H A Dahci_sunxi.c149 void __iomem *port_mmio = ahci_port_base(ap); in ahci_sunxi_start_engine() local
199 sunxi_setbits(port_mmio + PORT_CMD, PORT_CMD_START); in ahci_sunxi_start_engine()
H A Dacard-ahci.c288 void __iomem *port_mmio = ahci_port_base(ap); in acard_ahci_port_start() local
289 u32 cmd = readl(port_mmio + PORT_CMD); in acard_ahci_port_start()
H A Dahci.c803 void __iomem *port_mmio; in ahci_pci_init_controller() local
812 port_mmio = __ahci_port_base(hpriv, mv); in ahci_pci_init_controller()
814 writel(0, port_mmio + PORT_IRQ_MASK); in ahci_pci_init_controller()
817 tmp = readl(port_mmio + PORT_IRQ_STAT); in ahci_pci_init_controller()
820 writel(tmp, port_mmio + PORT_IRQ_STAT); in ahci_pci_init_controller()
/openbmc/u-boot/drivers/ata/
H A Dahci.c121 void __iomem *port_mmio = uc_priv->port[port].port_mmio; in ahci_link_up() local
129 tmp = readl(port_mmio + PORT_SCR_STAT); in ahci_link_up()
141 static void sunxi_dma_init(void __iomem *port_mmio) in sunxi_dma_init() argument
143 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400); in sunxi_dma_init()
189 void __iomem *port_mmio; in ahci_host_init() local
241 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i); in ahci_host_init()
242 port_mmio = (u8 *)uc_priv->port[i].port_mmio; in ahci_host_init()
246 tmp = readl(port_mmio + PORT_CMD); in ahci_host_init()
252 writel_with_flush(tmp, port_mmio + PORT_CMD); in ahci_host_init()
261 sunxi_dma_init(port_mmio); in ahci_host_init()
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H A Ddwc_ahsata.c116 struct sata_port_regs *port_mmio = NULL; in ahci_host_init() local
162 uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i); in ahci_host_init()
163 port_mmio = uc_priv->port[i].port_mmio; in ahci_host_init()
166 tmp = readl(&port_mmio->cmd); in ahci_host_init()
181 writel_with_flush(tmp, &port_mmio->cmd); in ahci_host_init()
190 while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR) in ahci_host_init()
201 tmp = readl(&port_mmio->cmd); in ahci_host_init()
202 writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd); in ahci_host_init()
206 while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD) in ahci_host_init()
216 tmp = readl(&port_mmio->ssts); in ahci_host_init()
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/openbmc/u-boot/board/highbank/
H A Dahci.c178 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; in ahci_link_up() local
189 writel(0x301, port_mmio + PORT_SCR_CTL); in ahci_link_up()
191 writel(0x300, port_mmio + PORT_SCR_CTL); in ahci_link_up()
196 tmp = readl(port_mmio + PORT_SCR_STAT); in ahci_link_up()
/openbmc/u-boot/include/
H A Dahci.h139 void __iomem *port_mmio; member