Searched refs:plv (Results 1 – 6 of 6) sorted by relevance
/openbmc/qemu/target/loongarch/ |
H A D | cpu_helper.c | 20 uint64_t plv = mmu_idx; in loongarch_map_tlb_entry() local 63 if (((tlb_rplv == 0) && (plv > tlb_plv)) || in loongarch_map_tlb_entry() 64 ((tlb_rplv == 1) && (plv != tlb_plv))) { in loongarch_map_tlb_entry() 185 uint32_t plv, base_c, base_v; in get_physical_address() local 197 plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT); in get_physical_address() 210 if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) { in get_physical_address()
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H A D | cpu.h | 448 uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); in is_va32() local 449 if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) { in is_va32()
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H A D | translate.h | 45 uint16_t plv; member
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/openbmc/qemu/target/loongarch/tcg/ |
H A D | op_helper.c | 93 uint64_t plv; in helper_rdtime_d() 96 plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV); in helper_rdtime_d() 97 if (extract64(env->CSR_MISC, R_CSR_MISC_DRDTL_SHIFT + plv, 1)) { in helper_rdtime_d()
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H A D | translate.c | 124 ctx->plv = ctx->base.tb->flags & HW_FLAGS_PLV_MASK; in loongarch_tr_init_disas_context() 126 ctx->mem_idx = ctx->plv; in loongarch_tr_init_disas_context()
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/openbmc/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_privileged.c.inc | 156 if (ctx->plv == MMU_PLV_USER) {
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