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Searched refs:pll_ctrl (Results 1 – 25 of 26) sorted by relevance

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/openbmc/linux/drivers/clk/zynq/
H A Dpll.c25 void __iomem *pll_ctrl; member
81 fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> in zynq_pll_recalc_rate()
103 reg = readl(clk->pll_ctrl); in zynq_pll_is_enabled()
129 reg = readl(clk->pll_ctrl); in zynq_pll_enable()
131 writel(reg, clk->pll_ctrl); in zynq_pll_enable()
159 reg = readl(clk->pll_ctrl); in zynq_pll_disable()
161 writel(reg, clk->pll_ctrl); in zynq_pll_disable()
185 void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, in clk_register_zynq_pll() argument
207 pll->pll_ctrl = pll_ctrl; in clk_register_zynq_pll()
214 reg = readl(pll->pll_ctrl); in clk_register_zynq_pll()
[all …]
/openbmc/u-boot/drivers/usb/host/
H A Dehci-vf.c62 void __iomem *pll_ctrl; in usb_power_config() local
66 pll_ctrl = &anadig->pll3_ctrl; in usb_power_config()
67 clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS); in usb_power_config()
68 setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE in usb_power_config()
73 pll_ctrl = &anadig->pll7_ctrl; in usb_power_config()
74 clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS); in usb_power_config()
75 setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE in usb_power_config()
/openbmc/linux/sound/soc/codecs/
H A Dda7213.c737 u8 pll_ctrl, pll_status; in da7213_dai_event() local
754 pll_ctrl = snd_soc_component_read(component, DA7213_PLL_CTRL); in da7213_dai_event()
755 if (!(pll_ctrl & DA7213_PLL_SRM_EN)) in da7213_dai_event()
759 if (pll_ctrl & DA7213_PLL_32K_MODE) { in da7213_dai_event()
782 pll_ctrl = snd_soc_component_read(component, DA7213_PLL_CTRL); in da7213_dai_event()
783 if (pll_ctrl & DA7213_PLL_32K_MODE) { in da7213_dai_event()
1438 u8 pll_ctrl, indiv_bits, indiv; in _da7213_set_component_pll() local
1484 pll_ctrl = indiv_bits; in _da7213_set_component_pll()
1491 DA7213_PLL_MODE_MASK, pll_ctrl); in _da7213_set_component_pll()
1496 pll_ctrl |= DA7213_PLL_SRM_EN; in _da7213_set_component_pll()
[all …]
H A Dda7219.c803 u8 pll_ctrl, pll_status; in da7219_dai_event() local
831 pll_ctrl = snd_soc_component_read(component, DA7219_PLL_CTRL); in da7219_dai_event()
832 if ((pll_ctrl & DA7219_PLL_MODE_MASK) != DA7219_PLL_MODE_SRM) in da7219_dai_event()
1224 u8 pll_ctrl, indiv_bits, indiv; in da7219_set_pll() local
1255 pll_ctrl = indiv_bits; in da7219_set_pll()
1260 pll_ctrl |= DA7219_PLL_MODE_BYPASS; in da7219_set_pll()
1263 DA7219_PLL_MODE_MASK, pll_ctrl); in da7219_set_pll()
1266 pll_ctrl |= DA7219_PLL_MODE_NORMAL; in da7219_set_pll()
1269 pll_ctrl |= DA7219_PLL_MODE_SRM; in da7219_set_pll()
1289 pll_ctrl); in da7219_set_pll()
H A Dda7218.c1399 u8 pll_ctrl, pll_status, refosc_cal; in da7218_dai_event() local
1441 pll_ctrl = snd_soc_component_read(component, DA7218_PLL_CTRL); in da7218_dai_event()
1442 if ((pll_ctrl & DA7218_PLL_MODE_MASK) != DA7218_PLL_MODE_SRM) in da7218_dai_event()
1861 u8 pll_ctrl, indiv_bits, indiv; in da7218_set_dai_pll() local
1892 pll_ctrl = indiv_bits; in da7218_set_dai_pll()
1897 pll_ctrl |= DA7218_PLL_MODE_BYPASS; in da7218_set_dai_pll()
1900 DA7218_PLL_MODE_MASK, pll_ctrl); in da7218_set_dai_pll()
1903 pll_ctrl |= DA7218_PLL_MODE_NORMAL; in da7218_set_dai_pll()
1906 pll_ctrl |= DA7218_PLL_MODE_SRM; in da7218_set_dai_pll()
1926 pll_ctrl); in da7218_set_dai_pll()
H A Dda7219-aad.c116 u8 pll_srm_sts, pll_ctrl, gain_ramp_ctrl, accdet_cfg8; in da7219_aad_hptest_work() local
147 pll_ctrl = snd_soc_component_read(component, DA7219_PLL_CTRL); in da7219_aad_hptest_work()
148 if ((pll_ctrl & DA7219_PLL_MODE_MASK) == DA7219_PLL_MODE_BYPASS) in da7219_aad_hptest_work()
316 ((pll_ctrl & DA7219_PLL_MODE_MASK) == DA7219_PLL_MODE_BYPASS)) in da7219_aad_hptest_work()
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti-phy.txt76 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
91 <0x4A096800 0x40>; /* pll_ctrl */
92 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
/openbmc/linux/include/linux/clk/
H A Dzynq.h15 void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
/openbmc/linux/arch/m68k/q40/
H A Dconfig.c255 pll->pll_ctrl = 0; in q40_get_rtc_pll()
270 if (!pll->pll_ctrl) { in q40_set_rtc_pll()
/openbmc/linux/drivers/media/dvb-frontends/
H A Ddib3000.h37 int (*tuner_pass_ctrl)(struct dvb_frontend *fe, int onoff, u8 pll_ctrl);
/openbmc/linux/include/uapi/linux/
H A Drtc.h61 int pll_ctrl; /* placeholder for fancier control */ member
/openbmc/linux/drivers/clk/bcm/
H A Dclk-iproc-pll.c716 const struct iproc_pll_ctrl *pll_ctrl, in iproc_pll_clk_setup() argument
731 if (WARN_ON(!pll_ctrl) || WARN_ON(!clk_ctrl)) in iproc_pll_clk_setup()
755 if (pll_ctrl->flags & IPROC_CLK_PLL_ASIU) { in iproc_pll_clk_setup()
761 if (pll_ctrl->flags & IPROC_CLK_PLL_SPLIT_STAT_CTRL) { in iproc_pll_clk_setup()
772 pll->ctrl = pll_ctrl; in iproc_pll_clk_setup()
H A Dclk-iproc.h204 const struct iproc_pll_ctrl *pll_ctrl,
/openbmc/u-boot/arch/m68k/include/asm/
H A Dimmap_5282.h89 typedef struct pll_ctrl { struct
H A Dimmap_520x.h176 typedef struct pll_ctrl { struct
H A Dimmap_5235.h206 typedef struct pll_ctrl { struct
H A Dimmap_5301x.h296 typedef struct pll_ctrl { struct
H A Dimmap_5275.h340 typedef struct pll_ctrl { struct
H A Dimmap_5329.h374 typedef struct pll_ctrl { struct
/openbmc/linux/drivers/video/fbdev/
H A Dsstfb.c1025 u8 pll_ctrl; in sst_set_pll_ics() local
1028 pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA); in sst_set_pll_ics()
1037 (pll_ctrl & 0xd8) in sst_set_pll_ics()
1048 (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A); in sst_set_pll_ics()
/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_display.c120 &hdmi->pll_ctrl); in sunxi_hdmi_hpd_detect()
772 writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
776 clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddisplay.h178 u32 pll_ctrl; /* 0x208 */ member
/openbmc/u-boot/arch/arm/dts/
H A Ddra7.dtsi1386 <0x4A096800 0x40>; /* pll_ctrl */
1387 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1494 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap5-l4.dtsi480 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
526 <0x6800 0x40>; /* pll_ctrl */
527 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
H A Ddra7-l4.dtsi291 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
375 <0x6800 0x40>; /* pll_ctrl */
376 reg-names = "phy_rx", "phy_tx", "pll_ctrl";

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