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Searched refs:pipe_bpp (Results 1 – 25 of 25) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dp.h32 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
77 void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
114 u32 pipe_bpp,
128 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
H A Dintel_dp.c702 u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp) in intel_dp_dsc_nearest_valid_bpp() argument
716 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); in intel_dp_dsc_nearest_valid_bpp()
751 u32 pipe_bpp, in intel_dp_dsc_get_output_bpp() argument
802 bits_per_pixel = intel_dp_dsc_nearest_valid_bpp(i915, bits_per_pixel, pipe_bpp); in intel_dp_dsc_get_output_bpp()
1176 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); in intel_dp_mode_valid() local
1196 pipe_bpp, 64) >> 4; in intel_dp_mode_valid()
1387 bpc = crtc_state->pipe_bpp / 3; in intel_dp_max_bpp()
1512 pipe_config->pipe_bpp = bpp; in intel_dp_compute_link_config_wide()
1674 int pipe_bpp; in intel_dp_dsc_compute_config() local
1687 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); in intel_dp_dsc_compute_config()
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H A Dg4x_hdmi.c45 if (crtc_state->pipe_bpp > 24) in intel_hdmi_prepare()
280 if (pipe_config->pipe_bpp > 24 && in ibx_enable_hdmi()
329 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
340 if (pipe_config->pipe_bpp > 24) { in cpt_enable_hdmi()
H A Dintel_dp_mst.c140 crtc_state->pipe_bpp = bpp; in intel_dp_mst_find_vcpi_slots_for_bpp()
165 intel_link_compute_m_n(crtc_state->pipe_bpp, in intel_dp_mst_compute_link_config()
241 crtc_state->pipe_bpp); in intel_dp_dsc_mst_compute_link_config()
347 limits.max_bpp = min(pipe_config->pipe_bpp, 24); in intel_dp_mst_compute_config()
973 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); in intel_dp_mst_mode_valid_ctx() local
983 pipe_bpp, 64) >> 4; in intel_dp_mst_mode_valid_ctx()
H A Dintel_fdi.c257 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
261 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, in ilk_fdi_compute_config()
268 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { in ilk_fdi_compute_config()
269 pipe_config->pipe_bpp -= 2*3; in ilk_fdi_compute_config()
272 pipe_config->pipe_bpp); in ilk_fdi_compute_config()
H A Dintel_lvds.c297 if (crtc_state->dither && crtc_state->pipe_bpp == 18) in intel_pre_enable_lvds()
438 if (lvds_bpp != crtc_state->pipe_bpp && !crtc_state->bw_constrained) { in intel_lvds_compute_config()
441 crtc_state->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()
442 crtc_state->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
H A Dintel_display.c2707 if (crtc_state->dither && crtc_state->pipe_bpp != 30) in i9xx_set_pipeconf()
2711 switch (crtc_state->pipe_bpp) { in i9xx_set_pipeconf()
2714 MISSING_CASE(crtc_state->pipe_bpp); in i9xx_set_pipeconf()
2919 pipe_config->pipe_bpp = 18; in i9xx_get_pipe_config()
2922 pipe_config->pipe_bpp = 24; in i9xx_get_pipe_config()
2925 pipe_config->pipe_bpp = 30; in i9xx_get_pipe_config()
3033 switch (crtc_state->pipe_bpp) { in ilk_set_pipeconf()
3036 MISSING_CASE(crtc_state->pipe_bpp); in ilk_set_pipeconf()
3119 switch (crtc_state->pipe_bpp) { in bdw_set_pipe_misc()
3135 MISSING_CASE(crtc_state->pipe_bpp); in bdw_set_pipe_misc()
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H A Dintel_hdmi.c927 static bool gcp_default_phase_possible(int pipe_bpp, in gcp_default_phase_possible() argument
932 switch (pipe_bpp) { in gcp_default_phase_possible()
1022 if (crtc_state->pipe_bpp > 24) in intel_hdmi_compute_gcp_infoframe()
1026 if (gcp_default_phase_possible(crtc_state->pipe_bpp, in intel_hdmi_compute_gcp_infoframe()
2088 bpc = max(crtc_state->pipe_bpp / 3, 8); in intel_hdmi_compute_bpc()
2137 crtc_state->pipe_bpp = min(crtc_state->pipe_bpp, bpc * 3); in intel_hdmi_compute_clock()
2141 bpc, crtc_state->pipe_bpp); in intel_hdmi_compute_clock()
H A Dhsw_ips.c198 if (crtc_state->pipe_bpp > 24) in hsw_crtc_state_ips_capable()
H A Dicl_dsi.c1535 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in gen11_dsi_get_config()
1580 if (crtc_state->pipe_bpp < 8 * 3) in gen11_dsi_dsc_compute_config()
1646 pipe_config->pipe_bpp = 24; in gen11_dsi_compute_config()
1648 pipe_config->pipe_bpp = 18; in gen11_dsi_compute_config()
H A Dintel_ddi.c398 switch (crtc_state->pipe_bpp) { in intel_ddi_set_dp_msa()
412 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_set_dp_msa()
489 switch (crtc_state->pipe_bpp) { in intel_ddi_transcoder_func_reg_val_get()
491 MISSING_CASE(crtc_state->pipe_bpp); in intel_ddi_transcoder_func_reg_val_get()
3700 pipe_config->pipe_bpp = 18; in intel_ddi_read_func_ctl()
3703 pipe_config->pipe_bpp = 24; in intel_ddi_read_func_ctl()
3706 pipe_config->pipe_bpp = 30; in intel_ddi_read_func_ctl()
3709 pipe_config->pipe_bpp = 36; in intel_ddi_read_func_ctl()
3815 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_ddi_get_config()
H A Dintel_crt.c447 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) { in hsw_crt_compute_config()
453 pipe_config->pipe_bpp = 24; in hsw_crt_compute_config()
H A Dvlv_dsi.c300 pipe_config->pipe_bpp = 24; in intel_dsi_compute_config()
302 pipe_config->pipe_bpp = 18; in intel_dsi_compute_config()
1040 pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc); in bxt_dsi_get_pipe_config()
H A Dintel_crtc_state_dump.c229 pipe_config->pipe_bpp, pipe_config->dither); in intel_crtc_state_dump()
H A Dintel_audio.c222 if (crtc_state->pipe_bpp == 36) { in audio_config_hdmi_get_n()
225 } else if (crtc_state->pipe_bpp == 30) { in audio_config_hdmi_get_n()
H A Dintel_display_debugfs.c587 str_yes_no(crtc_state->dither), crtc_state->pipe_bpp); in intel_crtc_info()
1450 seq_printf(m, "Current: %u\n", crtc_state->pipe_bpp / 3); in i915_current_bpc_show()
H A Dintel_panel.c665 if (DISPLAY_VER(dev_priv) < 4 && crtc_state->pipe_bpp == 18) in gmch_panel_fitting()
H A Dintel_modeset_setup.c321 conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3; in intel_modeset_update_connector_atomic_state()
H A Dintel_vdsc.c286 vdsc_cfg->bits_per_component = pipe_config->pipe_bpp / 3; in intel_dsc_compute_params()
H A Dintel_display_types.h1194 int pipe_bpp; member
H A Dg4x_dp.c403 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp); in intel_dp_get_config()
H A Dintel_psr.c1140 if (crtc_state->pipe_bpp > max_bpp) { in intel_psr2_config_valid()
1143 crtc_state->pipe_bpp, max_bpp); in intel_psr2_config_valid()
H A Dintel_bios.c3408 crtc_state->pipe_bpp = bpc * 3; in fill_dsc()
3410 crtc_state->dsc.compressed_bpp = min(crtc_state->pipe_bpp, in fill_dsc()
H A Dintel_tv.c1219 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
H A Dintel_sdvo.c1356 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()