Home
last modified time | relevance | path

Searched refs:phy_control (Results 1 – 24 of 24) sorted by relevance

/openbmc/linux/drivers/usb/phy/
H A Dphy-am335x-control.h5 struct phy_control { struct
6 void (*phy_power)(struct phy_control *phy_ctrl, u32 id, argument
8 void (*phy_wkup)(struct phy_control *phy_ctrl, u32 id, bool on); argument
11 static inline void phy_ctrl_power(struct phy_control *phy_ctrl, u32 id, in phy_ctrl_power()
17 static inline void phy_ctrl_wkup(struct phy_control *phy_ctrl, u32 id, bool on) in phy_ctrl_wkup()
22 struct phy_control *am335x_get_phy_control(struct device *dev);
H A Dphy-am335x-control.c16 struct phy_control phy_ctrl;
31 static void am335x_phy_wkup(struct phy_control *phy_ctrl, u32 id, bool on) in am335x_phy_wkup()
63 static void am335x_phy_power(struct phy_control *phy_ctrl, u32 id, in am335x_phy_power()
109 static const struct phy_control ctrl_am335x = {
128 struct phy_control *am335x_get_phy_control(struct device *dev) in am335x_get_phy_control()
154 const struct phy_control *phy_ctrl; in am335x_control_usb_probe()
H A Dphy-am335x.c18 struct phy_control *phy_ctrl;
/openbmc/qemu/hw/net/fsl_etsec/
H A Dmiim.c44 value = etsec->phy_control; in miim_read_cycle()
81 etsec->phy_control = value & ~(MII_BMCR_RESET | MII_BMCR_FD); in miim_write_cycle()
H A Detsec.h125 uint16_t phy_control; member
/openbmc/u-boot/drivers/usb/gadget/
H A Ddwc2_udc_otg_phy.c45 dev->pdata->phy_control(1); in otg_phy_init()
99 dev->pdata->phy_control(0); in otg_phy_off()
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_power_well.c1309 u32 phy_control = dev_priv->display.power.chv_phy_control; in assert_chv_phy_status() local
1337 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0) in assert_chv_phy_status()
1338 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0); in assert_chv_phy_status()
1340 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0) in assert_chv_phy_status()
1341 phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1); in assert_chv_phy_status()
1344 if (BITS_SET(phy_control, in assert_chv_phy_status()
1354 if (BITS_SET(phy_control, in assert_chv_phy_status()
1359 if (BITS_SET(phy_control, in assert_chv_phy_status()
1362 if (BITS_SET(phy_control, in assert_chv_phy_status()
1366 if (BITS_SET(phy_control, in assert_chv_phy_status()
[all …]
/openbmc/u-boot/include/usb/
H A Ddwc2_udc.h16 int (*phy_control)(int on); member
/openbmc/qemu/include/hw/net/
H A Dftgmac100.h66 uint32_t phy_control; member
H A Dimx_fec.h268 uint32_t phy_control; member
/openbmc/qemu/hw/net/
H A Dlan9118.c232 uint32_t phy_control; member
305 VMSTATE_UINT32(phy_control, lan9118_state),
420 s->phy_control = 0x3000; in phy_reset()
681 if (s->phy_control & 0x4000) { in do_tx_packet()
843 return s->phy_control; in do_phy_read()
879 s->phy_control = val & 0x7980; in do_phy_write()
H A Dimx_fec.c213 VMSTATE_UINT32(phy_control, IMXFECState),
272 s->phy_control = 0x3000; in imx_phy_reset()
301 val = s->phy_control; in imx_phy_read()
375 s->phy_control = val & 0x7980; in imx_phy_write()
H A Dftgmac100.c307 s->phy_control = (MII_BMCR_AUTOEN | MII_BMCR_FD | MII_BMCR_SPEED1000); in phy_reset()
321 val = s->phy_control; in do_phy_read()
389 s->phy_control = val & MII_BMCR_MASK; in do_phy_write()
1243 VMSTATE_UINT32(phy_control, FTGMAC100State),
/openbmc/u-boot/board/samsung/goni/
H A Dgoni.c187 .phy_control = s5pc1xx_phy_control,
/openbmc/linux/drivers/scsi/isci/
H A Dphy.c571 u32 phy_control; in sci_phy_start_sas_link_training() local
573 phy_control = readl(&iphy->link_layer_registers->phy_configuration); in sci_phy_start_sas_link_training()
574 phy_control |= SCU_SAS_PCFG_GEN_BIT(SATA_SPINUP_HOLD); in sci_phy_start_sas_link_training()
575 writel(phy_control, in sci_phy_start_sas_link_training()
H A Dregisters.h1367 u32 phy_control; member
/openbmc/u-boot/board/samsung/trats2/
H A Dtrats2.c255 .phy_control = s5pc210_phy_control,
/openbmc/linux/drivers/net/wireless/ath/carl9170/
H A Dwlan.h288 __le32 phy_control; member
H A Ddebug.c295 le16_to_cpu(txc->f.mac_control), le32_to_cpu(txc->f.phy_control), in carl9170_debugfs_format_frame()
H A Dtx.c927 txc->f.phy_control = phy_set; in carl9170_tx_apply_rateset()
/openbmc/u-boot/board/samsung/universal_c210/
H A Duniversal.c192 .phy_control = s5pc210_phy_control,
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c463 .phy_control = s5pc210_phy_control,
/openbmc/u-boot/board/samsung/trats/
H A Dtrats.c278 .phy_control = s5pc210_phy_control,
/openbmc/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c1354 u32 phy_control; in tg3_bmcr_reset() local
1360 phy_control = BMCR_RESET; in tg3_bmcr_reset()
1361 err = tg3_writephy(tp, MII_BMCR, phy_control); in tg3_bmcr_reset()
1367 err = tg3_readphy(tp, MII_BMCR, &phy_control); in tg3_bmcr_reset()
1371 if ((phy_control & BMCR_RESET) == 0) { in tg3_bmcr_reset()