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Searched refs:orr (Results 1 – 25 of 194) sorted by relevance

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/openbmc/linux/arch/arm/lib/
H A Dio-readsb.S39 orr r3, r3, r4, put_byte_1
41 orr r3, r3, r5, put_byte_2
43 orr r3, r3, r6, put_byte_3
47 orr r4, r4, r5, put_byte_1
49 orr r4, r4, r6, put_byte_2
51 orr r4, r4, ip, put_byte_3
55 orr r5, r5, r6, put_byte_1
57 orr r5, r5, ip, put_byte_2
59 orr r5, r5, lr, put_byte_3
62 orr r6, r6, ip, put_byte_1
[all …]
H A Dio-writesw-armv3.S25 orr r3, r3, r3, lsl #16
44 orr ip, ip, ip, lsr #16
48 orr ip, ip, ip, lsl #16
52 orr ip, ip, ip, lsr #16
56 orr ip, ip, ip, lsl #16
60 orr ip, ip, ip, lsr #16
64 orr ip, ip, ip, lsl #16
68 orr ip, ip, ip, lsr #16
72 orr ip, ip, ip, lsl #16
87 orr ip, ip, ip, lsr #16
[all …]
H A Dcsumpartialcopygeneric.S177 orr r4, r4, r5, lspush #24
179 orr r5, r5, r6, lspush #24
181 orr r6, r6, r7, lspush #24
183 orr r7, r7, r8, lspush #24
198 orr r4, r4, r5, lspush #24
200 orr r5, r5, r6, lspush #24
208 orr r4, r4, r5, lspush #24
229 orr r4, r4, r5, lspush #16
231 orr r5, r5, r6, lspush #16
233 orr r6, r6, r7, lspush #16
[all …]
H A Dio-readsw-armv3.S36 orr ip, ip, ip, lsl #8
45 orr r3, r3, r4, lsl #16
50 orr r4, r4, r5, lsl #16
55 orr r5, r5, r6, lsl #16
60 orr r6, r6, lr, lsl #16
76 orr r3, r3, r4, lsl #16
81 orr r4, r4, r5, lsl #16
91 orr r3, r3, r4, lsl #16
/openbmc/linux/drivers/scsi/arm/
H A Dacornscsi-io.S25 orr lr, lr, #0xff00
31 orr r3, r3, r4, lsl #16
33 orr r4, r4, r6, lsl #16
36 orr r5, r5, r6, lsl #16
38 orr r6, r6, ip, lsl #16
47 orr r3, r3, r4, lsl #16
49 orr r4, r4, r6, lsl #16
58 orr r3, r3, r4, lsl #16
83 orr r3, r3, r3, lsr #16
85 orr r4, r4, r4, lsl #16
[all …]
/openbmc/linux/arch/arm/mach-omap1/
H A Dsleep.S73 orr r4, r4, #TCMIF_ASM_BASE & 0x00ff0000
74 orr r4, r4, #TCMIF_ASM_BASE & 0x0000ff00
88 orr r5, r5, #SELF_REFRESH_MODE & 0xff000000
89 orr r5, r5, #SELF_REFRESH_MODE & 0x000000ff
94 orr r5, r5, #IDLE_EMIFS_REQUEST & 0xff
99 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x00ff0000
100 orr r4, r4, #CLKGEN_REG_ASM_BASE & 0x0000ff00
104 orr r5, r5, #OMAP1510_IDLE_CLOCK_DOMAINS & 0xff00
109 orr r3, r3, #OMAP1510_DEEP_SLEEP_REQUEST & 0xff00
113 orr r5, r5, #IDLE_WAIT_CYCLES & 0xff00
[all …]
H A Dsram.S26 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x00ff0000
27 orr r2, r2, #OMAP1_IO_ADDRESS(DPLL_CTL) & 0x0000ff00
30 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
31 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
37 orr r0, r0, #1 << 4 @ set lock bit again
44 orr r4, r4, #0x00ff
/openbmc/linux/arch/arm/mach-at91/
H A Dpm_suspend.S102 orr r9, r9, #AT91_SFRBU_25LDOCR_LP
108 orr r9, r9, r10
115 orr \reg, \reg, #0x200000
166 orr tmp1, tmp1, #UDDRC_PWRCTL_SELFREF_SW
187 orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
191 orr tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
197 orr tmp1, tmp1, #DDR3PHY_DXCCR_DXPDR
202 orr tmp1, tmp1, #DDR3PHY_ACIORC_ACPDD
203 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CKPDD_CK0
204 orr tmp1, tmp1, #DDR3PHY_ACIOCR_CSPDD_CS0
[all …]
/openbmc/linux/arch/arm64/lib/
H A Dstrlen.S97 orr tmp2, data1, REP8_7f
99 orr tmp4, data2, REP8_7f
126 orr tmp2, tmp1, tmp3
132 orr tmp2, tmp1, tmp3
138 orr tmp2, data1, REP8_7f
139 orr tmp4, data2, REP8_7f
155 orr tmp2, data1, REP8_7f
171 orr tmp2, data1, REP8_7f
173 orr tmp4, data2, REP8_7f
180 orr tmp2, data1, REP8_7f
[all …]
H A Dstrcmp.S73 orr tmp, tmp, REP8_7f
76 orr tmp, data1, REP8_7f
85 orr syndrome, diff, has_nul
117 orr data1, data1, tmp
118 orr data2, data2, tmp
142 orr data3, data3, tmp
144 orr tmp, data3, REP8_7f
159 orr tmp, data3, REP8_7f
170 orr syndrome, diff, tmp
182 orr syndrome, diff, has_nul
H A Dstrncmp.S80 orr tmp2, data1, #REP8_7f
90 orr syndrome, diff, has_nul
121 orr has_nul, has_nul, mask
139 orr tmp2, tmp3, #REP8_7f
142 orr syndrome, diff, has_nul
174 orr data1, data1, tmp2
175 orr data2, data2, tmp2
249 orr data2, data2, tmp1 /* 8 bytes from SRC2 combined from two regs.*/
252 orr tmp3, data1, #REP8_7f
255 orr tmp3, endloop, has_nul
[all …]
H A Dstrnlen.S75 orr tmp2, data1, #REP8_7f
77 orr tmp4, data2, #REP8_7f
81 orr tmp1, has_nul1, has_nul2
107 CPU_BE( orr tmp2, data2, #REP8_7f )
149 orr data1, data1, tmp2
150 orr data2a, data2, tmp2
/openbmc/linux/arch/arm64/include/asm/
H A Del2_setup.h82 orr x2, x2, x0 // If we don't have VHE, then
95 orr x2, x2, x0 // allow the EL1&0 translation
123 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1
124 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1
169 orr x0, x0, #(1 << 62)
181 orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
182 orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
190 orr x0, x0, #HFGxTR_EL2_nPIR_EL1
191 orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1
279 orr x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)
[all …]
/openbmc/u-boot/arch/arm/mach-orion5x/
H A Dlowlevel_init.S172 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
184 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
187 orr r0, r0, r1
194 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
206 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
209 orr r0, r0, r1
220 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
226 orr r0, r0, r1
231 orr r0, r0, #SDRAM_PAD_CTRL_WR_EN
237 orr r0, r0, r1
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dlowlevel_init.S57 orr r7, r7, $0x02
106 orr r8, r8, r9
162 orr r8, r8, r9
168 orr r7, r7, $0x01
185 orr r8, r8, r9
191 orr r7, r7, $0x01
210 orr r8, r8, $0x08
222 orr r8, r8, $0x01
234 orr r7, r7, $0x03
240 orr r7, r7, $0x01
[all …]
/openbmc/linux/arch/arm/mm/
H A Dproc-v7-2level.S46 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
47 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
80 orr r3, r3, r2
81 orr r3, r3, #PTE_EXT_AP0 | 2
148 ALT_SMP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_SMP)
149 ALT_UP(orr \ttbr0l, \ttbr0l, #TTB_FLAGS_UP)
150 ALT_SMP(orr \ttbr1, \ttbr1, #TTB_FLAGS_SMP)
151 ALT_UP(orr \ttbr1, \ttbr1, #TTB_FLAGS_UP)
H A Dproc-v6.S102 ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
103 ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
111 orr r1, r1, r2 @ insert into new context ID
164 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
165 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
201 orr r0, r0, #0x20
213 ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
214 ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
215 ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
216 ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
[all …]
/openbmc/u-boot/board/armltd/integrator/
H A Dlowlevel_init.S16 orr r1,r1,#CMMASK_RESET
45 orr r2,r2,#CMMASK_INIT_102
68 orr r2,r2,#CMMASK_CMxx6_COMMON
87 orr r1,r1,r2
160 orr r2, r1, r2, ASL#12 /* OR in column address lines */
161 orr r3, r2, r3, ASL#16 /* OR in number of banks */
162 orr r6, r6, r3 /* OR in size and CAS latency */
179 orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
/openbmc/u-boot/arch/arm/cpu/armv7/
H A Dstart.S99 orr r0, r0, #0xc0 @ disable FIQ and IRQ
194 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
195 orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
199 orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
205 orr r0, r0, #1 << 11 @ set bit #11
211 orr r0, r0, #1 << 4 @ set bit #4
217 orr r0, r0, #1 << 6 @ set bit #6
223 orr r0, r0, #1 << 11 @ set bit #11
228 orr r0, r0, #1 << 21 @ set bit #21
234 orr r0, r0, #1 << 22 @ set bit #22
[all …]
/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S248 orr r0, r0, #EP93XX_LED_RED_ON
261 orr r2, r2, r1
265 orr r2, r2, r1
269 orr r2, r2, r1
273 orr r2, r2, r1
277 orr r2, r2, r1
281 orr r2, r2, r1
339 orr r2, r11, #0x00008800
359 orr r2, r11, #0x00004600
376 orr r1, r1, #EP93XX_LED_GREEN_ON
[all …]
/openbmc/linux/arch/arm/mach-davinci/
H A Dsleep.S55 orr ip, ip, #DDR2_LPMODEN_BIT
59 orr ip, ip, #DDR2_MCLKSTOPEN_BIT
90 orr ip, ip, #PLLCTL_PLLPWRDN
95 orr ip, ip, #DEEPSLEEP_SLEEPENABLE_BIT
124 orr ip, ip, #PLLCTL_PLLRST
135 orr ip, ip, #PLLCTL_PLLEN
141 orr ip, ip, #PLLDIV_EN
180 orr ip, ip, r0
185 orr ip, ip, #0x1
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Ddebug_ll.S35 orr r1, r1, #1
58 orr r1, r1, #SC_CLKCTRL_CEN_PERI
73 orr r1, r1, #1
99 orr r1, r1, #SC_CLKCTRL_CEN_PERI
114 orr r1, r1, #1
124 orr r1, r1, #SC_CLKCTRL_CEN_PERI
139 orr r1, r1, #1
148 orr r1, r1, #SC_CLKCTRL_CEN_PERI
/openbmc/qemu/tests/tcg/arm/system/
H A Dboot.S112 orr r3, r4, r4
115 orr r3, r3, #2
124 orr r2, r2, r3 /* common bits */
125 orr r2, r2, #(1 << 15) /* AP[2] = 1 */
126 orr r2, r2, #(1 << 10) /* AP[0] = 1 => RO @ PL1 */
135 orr r2, r2, r3 /* common bits */
136 orr r2, r2, #(1 << 10) /* AP[0] = 1 => RW @ PL1 */
137 orr r2, r2, #(1 << 4) /* XN[4] => no execute */
/openbmc/qemu/tests/tcg/aarch64/system/
H A Dboot.S113 orr x1, x0, #3 /* ptr to stage 2 */
125 orr x1, x1, x3
135 orr x1, x1, x3
146 orr x1, x1, x3
186 orr x0, x0, x1 /* set bits */
198 orr x0, x0, #(3 << 20)
199 orr x0, x0, #(3 << 16)
/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dstart.S107 orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
133 orr x0, x0, #0x40
234 orr x0, x0, #1 << 44
244 orr x0, x0, #1 << 49
246 orr x0, x0, #3 << 25
248 orr x0, x0, #3 << 27
255 orr x0, x0, #1 << 59
264 orr x0, x0, #1 << 38
274 orr x0, x0, #1 << 4

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