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Searched refs:oprsz (Results 1 – 20 of 20) sorted by relevance

/openbmc/qemu/accel/tcg/
H A Dtcg-runtime-gvec.c27 static inline void clear_high(void *d, intptr_t oprsz, uint32_t desc) in clear_high() argument
32 if (unlikely(maxsz > oprsz)) { in clear_high()
33 for (i = oprsz; i < maxsz; i += sizeof(uint64_t)) { in clear_high()
41 intptr_t oprsz = simd_oprsz(desc); in HELPER() local
44 for (i = 0; i < oprsz; i += sizeof(uint8_t)) { in HELPER()
47 clear_high(d, oprsz, desc); in HELPER()
52 intptr_t oprsz = simd_oprsz(desc); in HELPER() local
55 for (i = 0; i < oprsz; i += sizeof(uint16_t)) { in HELPER()
58 clear_high(d, oprsz, desc); in HELPER()
63 intptr_t oprsz = simd_oprsz(desc); in HELPER() local
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/openbmc/qemu/tcg/
H A Dtcg-op-gvec.c38 static void check_size_align(uint32_t oprsz, uint32_t maxsz, uint32_t ofs) in check_size_align() argument
42 switch (oprsz) { in check_size_align()
46 tcg_debug_assert(oprsz <= maxsz); in check_size_align()
49 tcg_debug_assert(oprsz == maxsz); in check_size_align()
86 uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data) in simd_desc() argument
90 check_size_align(oprsz, maxsz, 0); in simd_desc()
106 oprsz = (oprsz / 8) - 1; in simd_desc()
114 if (oprsz == maxsz) { in simd_desc()
115 oprsz = 2; in simd_desc()
118 desc = deposit32(desc, SIMD_OPRSZ_SHIFT, SIMD_OPRSZ_BITS, oprsz); in simd_desc()
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/openbmc/qemu/include/tcg/
H A Dtcg-op-gvec-common.h26 uint32_t oprsz, uint32_t maxsz, int32_t data,
32 uint32_t oprsz, uint32_t maxsz, int32_t data,
38 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
44 uint32_t oprsz, uint32_t maxsz, int32_t data,
51 uint32_t cofs, uint32_t oprsz, uint32_t maxsz,
58 uint32_t cofs, uint32_t xofs, uint32_t oprsz,
64 TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz,
70 uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz,
78 uint32_t oprsz, uint32_t maxsz, int32_t data,
231 uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
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H A Dtcg-gvec-desc.h43 uint32_t simd_desc(uint32_t oprsz, uint32_t maxsz, int32_t data);
/openbmc/qemu/target/loongarch/tcg/
H A Dvec_helper.c26 int oprsz = simd_oprsz(desc); \
28 for (i = 0; i < oprsz / (BIT / 8); i++) { \
43 int oprsz = simd_oprsz(desc); in HELPER() local
45 for (i = 0; i < oprsz / 16 ; i++) { in HELPER()
61 int oprsz = simd_oprsz(desc); in HELPER() local
63 for (i = 0; i < oprsz / 16; i++) { in HELPER()
79 int oprsz = simd_oprsz(desc); in HELPER() local
81 for (i = 0; i < oprsz / 16; i ++) { in HELPER()
97 int oprsz = simd_oprsz(desc); in HELPER() local
99 for (i = 0; i < oprsz / 16; i++) { in HELPER()
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/openbmc/qemu/target/arm/tcg/
H A Dsme_helper.c101 int i, oprsz = simd_oprsz(desc); \
102 for (i = 0; i < oprsz; ) { \
120 int i, oprsz = simd_oprsz(desc) / 8; in DO_MOVA_C() local
125 for (i = 0; i < oprsz; i++) { in DO_MOVA_C()
134 int i, oprsz = simd_oprsz(desc) / 16; in HELPER() local
143 for (i = 0; i < oprsz; i++) { in HELPER()
158 int i, oprsz = simd_oprsz(desc); \
159 for (i = 0; i < oprsz; ) { \
177 int i, oprsz = simd_oprsz(desc) / 8; in DO_MOVA_Z() local
182 for (i = 0; i < oprsz; i++) { in DO_MOVA_Z()
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H A Dvec_helper.c1213 intptr_t i, oprsz = simd_oprsz(desc); \
1215 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
1218 clear_tail(d, oprsz, simd_maxsz(desc)); \
1371 intptr_t i, oprsz = simd_oprsz(desc); \
1373 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
1376 clear_tail(d, oprsz, simd_maxsz(desc)); \
1526 intptr_t i, oprsz = simd_oprsz(desc); \
1528 for (i = 0; i < oprsz / sizeof(TYPE); i++) { \
1531 clear_tail(d, oprsz, simd_maxsz(desc)); \
1555 intptr_t i, j, oprsz = simd_oprsz(desc); \ in DO_MULADD()
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H A Dsve_helper.c1347 intptr_t i, j, oprsz = simd_oprsz(desc); \
1354 for (i = 0; i < oprsz / sizeof(TYPE); i += 16 / sizeof(TYPE)) { \
1481 intptr_t oprsz = simd_oprsz(desc), segment = 16 / sizeof(TYPE); \
1484 for (i = 0; i < oprsz / sizeof(TYPE); i += segment) { \
1517 intptr_t i, j, oprsz = simd_oprsz(desc); \
1520 for (i = 0; i < oprsz; i += 16) { \
1563 intptr_t i, j, oprsz = simd_oprsz(desc); \
1566 for (i = 0; i < oprsz; i += 16) { \
2584 intptr_t i, oprsz = simd_oprsz(desc); in HELPER() local
2586 for (i = 0; i < oprsz; i += sizeof(int8_t)) { in HELPER()
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H A Dtranslate-mve.c1518 int64_t c, uint32_t oprsz, uint32_t maxsz) in gen_gvec_vmovi() argument
1520 tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, c); in gen_gvec_vmovi()
1611 int64_t shift, uint32_t oprsz, uint32_t maxsz) in do_gvec_shri_s() argument
1621 tcg_gen_gvec_sari(vece, dofs, aofs, shift, oprsz, maxsz); in do_gvec_shri_s()
1625 int64_t shift, uint32_t oprsz, uint32_t maxsz) in do_gvec_shri_u() argument
1633 tcg_gen_gvec_dup_imm(vece, dofs, oprsz, maxsz, 0); in do_gvec_shri_u()
1635 tcg_gen_gvec_shri(vece, dofs, aofs, shift, oprsz, maxsz); in do_gvec_shri_u()
1730 int64_t shift, uint32_t oprsz, uint32_t maxsz)
1734 tcg_gen_gvec_shli(ovece, dofs, aofs, ibits, oprsz, maxsz);
1735 tcg_gen_gvec_sari(ovece, dofs, dofs, ibits - shift, oprsz, maxsz);
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H A Dgengvec64.c153 uint32_t a, uint32_t oprsz, uint32_t maxsz) in gen_gvec_eor3() argument
162 tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); in gen_gvec_eor3()
179 uint32_t a, uint32_t oprsz, uint32_t maxsz) in gen_gvec_bcax() argument
188 tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); in gen_gvec_bcax()
H A Dtranslate-neon.c839 uint32_t oprsz, uint32_t maxsz) \ in DO_3SAME()
841 tcg_gen_gvec_bitsel(vece, rd_ofs, O1, O2, O3, oprsz, maxsz); \ in DO_3SAME()
885 uint32_t oprsz, uint32_t maxsz) \
887 tcg_gen_gvec_cmp(COND, vece, rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz); \
899 uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz) \
901 tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz, 0, FUNC); \
980 uint32_t oprsz, uint32_t maxsz) \
984 oprsz, maxsz, 0, FUNC); \
1452 int64_t c, uint32_t oprsz, uint32_t maxsz) in gen_VMOV_1r() argument
1454 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); in gen_VMOV_1r()
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H A Dtranslate-a64.h197 uint32_t a, uint32_t oprsz, uint32_t maxsz);
199 uint32_t a, uint32_t oprsz, uint32_t maxsz);
H A Dtranslate-sve.c581 uint32_t a, uint32_t oprsz, uint32_t maxsz) in TRANS_FEAT()
584 tcg_gen_gvec_bitsel(vece, d, a, n, m, oprsz, maxsz); in TRANS_FEAT()
610 uint32_t a, uint32_t oprsz, uint32_t maxsz) in gen_bsl1n() argument
619 tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); in gen_bsl1n()
654 uint32_t a, uint32_t oprsz, uint32_t maxsz) in gen_bsl2n() argument
663 tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); in gen_bsl2n()
683 uint32_t a, uint32_t oprsz, uint32_t maxsz) in gen_nbsl() argument
692 tcg_gen_gvec_4(d, n, m, a, oprsz, maxsz, &op); in gen_nbsl()
1637 unsigned oprsz = size_for_gvec(setsz / 8); in do_predset() local
1639 if (oprsz * 8 == setsz) { in do_predset()
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H A Dtranslate-a64.c6934 int64_t c, uint32_t oprsz, uint32_t maxsz) in gen_movi() argument
6936 tcg_gen_gvec_dup_imm(MO_64, dofs, oprsz, maxsz, c); in gen_movi()
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_vec.c.inc7 static bool check_vec(DisasContext *ctx, uint32_t oprsz)
9 if ((oprsz == 16) && ((ctx->base.tb->flags & HW_FLAGS_EUEN_SXE) == 0)) {
14 if ((oprsz == 32) && ((ctx->base.tb->flags & HW_FLAGS_EUEN_ASXE) == 0)) {
22 static bool gen_vvvv_ptr_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
25 if (!check_vec(ctx, oprsz)) {
34 oprsz, ctx->vl / 8, 0, fn);
50 static bool gen_vvvv_vl(DisasContext *ctx, arg_vvvv *a, uint32_t oprsz,
53 if (!check_vec(ctx, oprsz)) {
61 oprsz, ctx->vl / 8, 0, fn);
77 static bool gen_vvv_ptr_vl(DisasContext *ctx, arg_vvv *a, uint32_t oprsz,
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/openbmc/qemu/target/riscv/
H A Dvector_helper.c931 intptr_t oprsz = simd_oprsz(desc); local
934 for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
941 intptr_t oprsz = simd_oprsz(desc); in HELPER() local
944 for (i = 0; i < oprsz; i += sizeof(uint16_t)) { in HELPER()
951 intptr_t oprsz = simd_oprsz(desc); in HELPER() local
954 for (i = 0; i < oprsz; i += sizeof(uint32_t)) { in HELPER()
961 intptr_t oprsz = simd_oprsz(desc); in HELPER() local
964 for (i = 0; i < oprsz; i += sizeof(uint64_t)) { in HELPER()
/openbmc/qemu/target/sparc/
H A Dtranslate.c950 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) in gen_op_fchksm16() argument
961 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &op); in gen_op_fchksm16()
978 uint32_t bofs, uint32_t oprsz, uint32_t maxsz) in gen_op_fmean16() argument
989 tcg_gen_gvec_3(dofs, aofs, bofs, oprsz, maxsz, &op); in gen_op_fmean16()
/openbmc/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc1338 TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
1366 tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]);
1460 int64_t c, uint32_t oprsz, uint32_t maxsz)
1463 tcg_gen_gvec_rsubs(vece, dofs, aofs, tmp, oprsz, maxsz);
/openbmc/qemu/target/i386/tcg/
H A Demit.c.inc2589 * Because oprsz is 8, we see this here even for SSE; but more in general,
2590 * it disqualifies using oprsz < maxsz to emulate VEX128.
/openbmc/qemu/target/s390x/tcg/
H A Dtranslate_vx.c.inc31 * On s390x, the operand size (oprsz) and the maximum size (maxsz) are