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Searched refs:opc2 (Results 1 – 24 of 24) sorted by relevance

/openbmc/qemu/target/ppc/translate/
H A Dvmx-ops.c.inc1 #define GEN_VXFORM(name, opc2, opc3) \
2 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
4 #define GEN_VXFORM_207(name, opc2, opc3) \
5 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ALTIVEC_207)
7 #define GEN_VXFORM_300(name, opc2, opc3) \
8 GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA300)
10 #define GEN_VXFORM_300_EXT(name, opc2, opc3, inval) \
11 GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
13 #define GEN_VXFORM_300_EO(name, opc2, opc3, opc4) \
14 GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
[all …]
H A Dvsx-ops.c.inc12 #define GEN_XX1FORM(name, opc2, opc3, fl2) \
13 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
14 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
16 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
17 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
18 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
20 #define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
21 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
22 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
24 #define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
[all …]
H A Dspe-ops.c.inc6 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
85 #define GEN_SPEOP_LDST(name, opc2, sh) \
86 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
H A Dfp-ops.c.inc27 #define GEN_STXF(name, stop, opc2, opc3, type) \
28 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
H A Dvmx-impl.c.inc201 #define GEN_VXFORM_V(name, vece, tcg_op, opc2, opc3) \
216 #define GEN_VXFORM(name, opc2, opc3) \
230 #define GEN_VXFORM_TRANS(name, opc2, opc3) \
240 #define GEN_VXFORM_ENV(name, opc2, opc3) \
254 #define GEN_VXFORM3(name, opc2, opc3) \
329 #define GEN_VXFORM_HETRO(name, opc2, opc3) \
1093 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
1107 #define GEN_VXRFORM(name, opc2, opc3) \
1108 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
1109 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
[all …]
H A Dspe-impl.c.inc42 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
765 #define GEN_SPEOP_LDST(name, opc2, sh) \
H A Dfp-impl.c.inc855 #define GEN_STXF(name, stop, opc2, opc3, type) \
/openbmc/qemu/target/arm/
H A Dhelper.c634 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
639 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
651 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
659 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
673 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
683 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
685 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
687 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
689 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
692 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
[all …]
H A Dcortex-regs.c31 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
35 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
39 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
42 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
45 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
48 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
54 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
60 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
66 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
H A Ddebug_helper.c948 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
952 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
955 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
960 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
971 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
981 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
985 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
990 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0,
999 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
1009 .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
[all …]
H A Dsyndrome.h171 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, in syn_cp14_rt_trap() argument
177 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp14_rt_trap()
181 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, in syn_cp15_rt_trap() argument
187 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp15_rt_trap()
H A Dcpregs.h171 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ argument
173 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
864 uint8_t opc2; member
1077 uint8_t opc2, in arm_cpreg_encoding_in_idspace() argument
1091 arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, in arm_cpreg_in_idspace()
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c481 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
486 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
489 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
492 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
495 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
498 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
502 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
506 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
514 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
[all …]
H A Dcpu32.c197 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, in arm1026_initfn()
337 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
339 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
388 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
391 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
394 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
397 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
400 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
402 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
404 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
[all …]
H A Da32.decode50 &mcr cp opc1 crn crm opc2 rt
546 @mcr ---- .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 &mcr
H A Dt32.decode48 &mcr !extern cp opc1 crn crm opc2 rt
707 @mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4
H A Dtranslate.c2933 int opc1, int crn, int crm, int opc2, in do_coproc_insn() argument
2936 uint32_t key = ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2); in do_coproc_insn()
2957 syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, in do_coproc_insn()
2966 syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, in do_coproc_insn()
3048 crm, opc2, s->ns ? "non-secure" : "secure"); in do_coproc_insn()
3602 do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, in trans_MCR()
3612 do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, in trans_MRC()
H A Dneon-dp.decode420 # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c562 int regno = ri->opc2 & 3; in icv_ap_read()
574 int regno = ri->opc2 & 3; in icv_ap_write()
666 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_read()
669 trace_gicv3_icv_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_read()
680 trace_gicv3_icv_igrpen_write(ri->opc2 & 1 ? 1 : 0, in icv_igrpen_write()
683 enbit = ri->opc2 & 1 ? ICH_VMCR_EL2_VENG1_SHIFT : ICH_VMCR_EL2_VENG0_SHIFT; in icv_igrpen_write()
1832 int regno = ri->opc2 & 3; in icc_ap_read()
1854 int regno = ri->opc2 & 3; in icc_ap_write()
2103 int grp = ri->opc2 & 1 ? GICV3_G1 : GICV3_G0; in icc_igrpen_read()
2115 trace_gicv3_icc_igrpen_read(ri->opc2 & 1 ? 1 : 0, in icc_igrpen_read()
[all …]
H A Darm_gicv3_kvm.c734 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
/openbmc/qemu/target/ppc/
H A Dtranslate.c1432 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ argument
1433 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1435 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ argument
1436 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1438 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ argument
1439 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1441 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ argument
1442 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1444 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ argument
1445 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
[all …]
H A Dinternal.h100 EXTRACT_HELPER(opc2, 1, 5);
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc450 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
455 inst = (sa & 32 ? opc2 : opc1);
/openbmc/linux/Documentation/virt/kvm/
H A Dapi.rst2489 0x4020 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>