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Searched refs:opc1 (Results 1 – 20 of 20) sorted by relevance

/openbmc/qemu/target/arm/
H A Dcortex-regs.c31 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
35 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
39 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
42 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
45 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
48 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
51 .cp = 15, .opc1 = 0, .crm = 15,
54 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
57 .cp = 15, .opc1 = 1, .crm = 15,
60 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
[all …]
H A Dhelper.c634 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
639 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
651 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
659 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
673 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
683 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
685 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
687 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
689 .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
692 .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
[all …]
H A Ddebug_helper.c948 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
952 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
955 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
960 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
971 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
981 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
985 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
990 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0,
999 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
1009 .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
[all …]
H A Dsyndrome.h171 static inline uint32_t syn_cp14_rt_trap(int cv, int cond, int opc1, int opc2, in syn_cp14_rt_trap() argument
177 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp14_rt_trap()
181 static inline uint32_t syn_cp15_rt_trap(int cv, int cond, int opc1, int opc2, in syn_cp15_rt_trap() argument
187 | (cv << 24) | (cond << 20) | (opc2 << 17) | (opc1 << 14) in syn_cp15_rt_trap()
191 static inline uint32_t syn_cp14_rrt_trap(int cv, int cond, int opc1, int crm, in syn_cp14_rrt_trap() argument
197 | (cv << 24) | (cond << 20) | (opc1 << 16) in syn_cp14_rrt_trap()
201 static inline uint32_t syn_cp15_rrt_trap(int cv, int cond, int opc1, int crm, in syn_cp15_rrt_trap() argument
207 | (cv << 24) | (cond << 20) | (opc1 << 16) in syn_cp15_rrt_trap()
H A Dcpregs.h171 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ argument
173 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
863 uint8_t opc1; member
1076 static inline bool arm_cpreg_encoding_in_idspace(uint8_t opc0, uint8_t opc1, in arm_cpreg_encoding_in_idspace() argument
1080 return opc0 == 3 && (opc1 == 0 || opc1 == 1 || opc1 == 3) && in arm_cpreg_encoding_in_idspace()
1091 arm_cpreg_encoding_in_idspace(ri->opc0, ri->opc1, ri->opc2, in arm_cpreg_in_idspace()
1134 return ri->opc1 == 4 || ri->opc1 == 5; in arm_cpreg_traps_in_nv()
/openbmc/qemu/target/arm/tcg/
H A Dcpu32.c197 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, in arm1026_initfn()
337 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
339 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
388 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
391 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
394 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
397 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
400 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
402 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
404 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
[all …]
H A Dcpu64.c481 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
486 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
489 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
492 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
495 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
498 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
502 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
506 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
514 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
[all …]
H A Da32.decode50 &mcr cp opc1 crn crm opc2 rt
51 &mcrr cp opc1 crm rt rt2
546 @mcr ---- .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4 &mcr
547 @mcrr ---- .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4 &mcrr
H A Dt32.decode48 &mcr !extern cp opc1 crn crm opc2 rt
49 &mcrr !extern cp opc1 crm rt rt2
707 @mcr .... .... opc1:3 . crn:4 rt:4 cp:4 opc2:3 . crm:4
708 @mcrr .... .... .... rt2:4 rt:4 cp:4 opc1:4 crm:4
H A Dtranslate.c2933 int opc1, int crn, int crm, int opc2, in do_coproc_insn() argument
2936 uint32_t key = ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2); in do_coproc_insn()
2954 syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, in do_coproc_insn()
2957 syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, in do_coproc_insn()
2963 syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, in do_coproc_insn()
2966 syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, in do_coproc_insn()
3041 isread ? "read" : "write", cpnum, opc1, crm, in do_coproc_insn()
3047 isread ? "read" : "write", cpnum, opc1, crn, in do_coproc_insn()
3602 do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, in trans_MCR()
3612 do_coproc_insn(s, a->cp, false, a->opc1, a->crn, a->crm, a->opc2, in trans_MRC()
[all …]
H A Dneon-dp.decode420 # 1111 001 11 D 11 size:2 opc1:2 Vd:4 0 opc2:4 q:1 M 0 Vm:4
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2443 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0,
2455 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 0,
2461 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1,
2467 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 2,
2473 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3,
2480 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 4,
2488 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0,
2495 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1,
2501 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 3,
2507 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5,
[all …]
H A Darm_gicv3_kvm.c734 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
/openbmc/linux/arch/x86/kernel/
H A Duprobes.c587 return auprobe->branch.opc1 == 0xe8; in branch_is_call()
623 switch (auprobe->branch.opc1) { in check_jmp_cond()
718 u8 opc1 = OPCODE1(insn); in branch_setup_xol_ops() local
722 switch (opc1) { in branch_setup_xol_ops()
740 opc1 = OPCODE2(insn) - 0x10; in branch_setup_xol_ops()
743 if (!is_cond_jmp_opcode(opc1)) in branch_setup_xol_ops()
758 auprobe->branch.opc1 = opc1; in branch_setup_xol_ops()
769 u8 opc1 = OPCODE1(insn), reg_offset = 0; in push_setup_xol_ops() local
771 if (opc1 < 0x50 || opc1 > 0x57) in push_setup_xol_ops()
783 switch (opc1) { in push_setup_xol_ops()
[all …]
/openbmc/linux/arch/s390/kernel/
H A Duprobes.c228 u8 opc1 : 4; member
279 switch (insn->opc1) { in handle_insn_ril()
286 switch (insn->opc1) { in handle_insn_ril()
323 switch (insn->opc1) { in handle_insn_ril()
/openbmc/linux/arch/x86/include/asm/
H A Duprobes.h37 u8 opc1; member
/openbmc/qemu/target/ppc/
H A Dtranslate.c1432 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \ argument
1433 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
1435 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \ argument
1436 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
1438 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \ argument
1439 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
1441 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \ argument
1442 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
1444 #define GEN_HANDLER_E_2(name, opc1, opc2, opc3, opc4, inval, type, type2) \ argument
1445 GEN_OPCODE3(name, opc1, opc2, opc3, opc4, inval, type, type2)
[all …]
H A Dinternal.h98 EXTRACT_HELPER(opc1, 26, 6);
/openbmc/qemu/tcg/mips/
H A Dtcg-target.c.inc450 static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2,
455 inst = (sa & 32 ? opc2 : opc1);
/openbmc/linux/Documentation/virt/kvm/
H A Dapi.rst2489 0x4020 0000 000F <zero:1> <crn:4> <crm:4> <opc1:4> <opc2:3>
2493 0x4030 0000 000F <zero:1> <zero:4> <crm:4> <opc1:4> <zero:3>