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Searched refs:nest_regs (Results 1 – 6 of 6) sorted by relevance

/openbmc/qemu/hw/pci-host/
H A Dpnv_phb3_pbcq.c33 return pbcq->nest_regs[offset]; in pnv_pbcq_nest_xscom_read()
60 uint64_t bar_en = pbcq->nest_regs[PBCQ_NEST_BAR_EN]; in pnv_pbcq_update_map()
91 bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR0] >> 14; in pnv_pbcq_update_map()
92 mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK0]; in pnv_pbcq_update_map()
101 bar = pbcq->nest_regs[PBCQ_NEST_MMIO_BAR1] >> 14; in pnv_pbcq_update_map()
102 mask = pbcq->nest_regs[PBCQ_NEST_MMIO_MASK1]; in pnv_pbcq_update_map()
111 bar = pbcq->nest_regs[PBCQ_NEST_PHB_BAR] >> 14; in pnv_pbcq_update_map()
132 if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] & in pnv_pbcq_nest_xscom_write()
137 pbcq->nest_regs[reg] = val & 0xffffffffc0000000ull; in pnv_pbcq_nest_xscom_write()
140 if (pbcq->nest_regs[PBCQ_NEST_BAR_EN] & PBCQ_NEST_BAR_EN_PHB) { in pnv_pbcq_nest_xscom_write()
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H A Dpnv_phb4_pec.c38 return pec->nest_regs[reg]; in pnv_pec_nest_xscom_read()
49 pec->nest_regs[reg] = val & PPC_BITMASK(0, 25); in pnv_pec_nest_xscom_write()
52 pec->nest_regs[reg] = val & PPC_BITMASK(0, 11); in pnv_pec_nest_xscom_write()
55 pec->nest_regs[reg] = val & PPC_BITMASK(0, 16); in pnv_pec_nest_xscom_write()
58 pec->nest_regs[reg] = val & PPC_BITMASK(0, 37); in pnv_pec_nest_xscom_write()
61 pec->nest_regs[reg] = val & PPC_BITMASK(0, 6); in pnv_pec_nest_xscom_write()
64 pec->nest_regs[reg] = val & PPC_BITMASK(0, 15); in pnv_pec_nest_xscom_write()
67 pec->nest_regs[reg] = val & PPC_BITMASK(0, 48); in pnv_pec_nest_xscom_write()
71 pec->nest_regs[reg] = val & PPC_BITMASK(0, 24); in pnv_pec_nest_xscom_write()
74 pec->nest_regs[reg] = val & PPC_BITMASK(0, 41); in pnv_pec_nest_xscom_write()
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H A Dpnv_phb4.c858 return phb->nest_regs[reg]; in pnv_pec_stk_nest_xscom_read()
911 uint64_t bar_en = phb->nest_regs[PEC_NEST_STK_BAR_EN]; in pnv_pec_phb_update_map()
948 bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0] >> 8; in pnv_pec_phb_update_map()
949 mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR0_MASK]; in pnv_pec_phb_update_map()
960 bar = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1] >> 8; in pnv_pec_phb_update_map()
961 mask = phb->nest_regs[PEC_NEST_STK_MMIO_BAR1_MASK]; in pnv_pec_phb_update_map()
972 bar = phb->nest_regs[PEC_NEST_STK_PHB_REGS_BAR] >> 8; in pnv_pec_phb_update_map()
981 bar = phb->nest_regs[PEC_NEST_STK_INT_BAR] >> 8; in pnv_pec_phb_update_map()
1002 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] = val & PPC_BITMASK(0, 27); in pnv_pec_stk_nest_xscom_write()
1005 phb->nest_regs[PEC_NEST_STK_PCI_NEST_FIR] &= val; in pnv_pec_stk_nest_xscom_write()
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H A Dpnv_phb3.c361 baren = pbcq->nest_regs[PBCQ_NEST_BAR_EN]; in pnv_phb3_remap_irqs()
373 pbcq->nest_regs[PBCQ_NEST_LSI_SRC_ID]) << 3; in pnv_phb3_remap_irqs()
385 pbcq->nest_regs[PBCQ_NEST_IRSN_COMPARE]); in pnv_phb3_remap_irqs()
387 pbcq->nest_regs[PBCQ_NEST_IRSN_MASK]); in pnv_phb3_remap_irqs()
/openbmc/qemu/include/hw/pci-host/
H A Dpnv_phb4.h121 uint64_t nest_regs[PHB4_PEC_NEST_STK_REGS_COUNT]; member
179 uint64_t nest_regs[PHB4_PEC_NEST_REGS_COUNT]; member
H A Dpnv_phb3.h86 uint64_t nest_regs[PBCQ_NEST_REGS_COUNT]; member