Home
last modified time | relevance | path

Searched refs:n_shift (Results 1 – 20 of 20) sorted by relevance

/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c368 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
370 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
372 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
374 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
376 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
378 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
380 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
382 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
384 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c437 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
439 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
441 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
443 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
445 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
447 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
449 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
451 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
453 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c417 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
419 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
421 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
423 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
425 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
427 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
429 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
431 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
433 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/openbmc/linux/drivers/clk/ingenic/
H A Dx1830-cgu.c121 .n_shift = 14,
144 .n_shift = 14,
167 .n_shift = 14,
190 .n_shift = 14,
H A Dx1000-cgu.c226 .n_shift = 18,
249 .n_shift = 18,
369 .n_shift = 0,
H A Djz4760-cgu.c101 .n_shift = 18,
126 .n_shift = 18,
H A Dcgu.h57 u8 n_shift, n_bits, n_offset; member
H A Djz4770-cgu.c111 .n_shift = 18,
135 .n_shift = 18,
H A Djz4725b-cgu.c63 .n_shift = 18,
H A Djz4740-cgu.c78 .n_shift = 18,
H A Djz4755-cgu.c60 .n_shift = 18,
H A Dcgu.c97 n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0); in ingenic_pll_recalc_rate()
225 ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift); in ingenic_pll_set_rate()
226 ctl |= (n - pll_info->n_offset) << pll_info->n_shift; in ingenic_pll_set_rate()
H A Djz4780-cgu.c279 .n_shift = 13, \
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c577 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
579 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
581 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
583 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
585 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
587 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
589 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
591 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
593 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
595 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c646 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
648 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
650 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
652 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
654 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
656 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
658 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
660 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
662 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
664 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dclock.c103 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask; in clock_ll_read_pll()
147 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
551 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask); in clock_get_rate()
602 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift); in clock_set_rate()
603 base_reg |= n << pllinfo->n_shift; in clock_set_rate()
H A Dcpu.c188 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift); in pllx_set_rate()
/openbmc/linux/fs/reiserfs/
H A Ddo_balan.c763 int n_shift, n_rem, r_zeroes_number, version; in balance_leaf_paste_right_shift() local
780 n_shift = tb->rbytes - tb->insert_size[0]; in balance_leaf_paste_right_shift()
781 if (n_shift < 0) in balance_leaf_paste_right_shift()
782 n_shift = 0; in balance_leaf_paste_right_shift()
789 leaf_shift_right(tb, tb->rnum[0], n_shift); in balance_leaf_paste_right_shift()
825 leaf_paste_in_buffer(&bi, 0, n_shift, tb->insert_size[0] - n_rem, in balance_leaf_paste_right_shift()
1073 int n_shift, n_rem, r_zeroes_number, shift; in balance_leaf_new_nodes_paste_shift() local
1096 n_shift = tb->sbytes[i] - tb->insert_size[0]; in balance_leaf_new_nodes_paste_shift()
1097 if (n_shift < 0) in balance_leaf_new_nodes_paste_shift()
1098 n_shift = 0; in balance_leaf_new_nodes_paste_shift()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h391 u32 n_shift:5; /* DIVN_SHIFT */ member
/openbmc/linux/drivers/gpu/drm/omapdrm/
H A Domap_gem.c392 const int n_shift = priv->usergart[fmt].height_shift; in omap_gem_fault_2d() local
409 base_pgoff = round_down(pgoff, m << n_shift); in omap_gem_fault_2d()
426 base_pgoff = (base_pgoff >> n_shift) * slots; in omap_gem_fault_2d()
433 slots = min(slots - (off << n_shift), n); in omap_gem_fault_2d()
434 base_pgoff += off << n_shift; in omap_gem_fault_2d()