| /openbmc/linux/drivers/tty/serial/ |
| H A D | mcf.c | 202 unsigned char mr1, mr2; in mcf_set_termios() local
212 mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR; in mcf_set_termios()
216 case CS5: mr1 |= MCFUART_MR1_CS5; break; in mcf_set_termios()
217 case CS6: mr1 |= MCFUART_MR1_CS6; break; in mcf_set_termios()
218 case CS7: mr1 |= MCFUART_MR1_CS7; break; in mcf_set_termios()
220 default: mr1 |= MCFUART_MR1_CS8; break; in mcf_set_termios()
226 mr1 |= MCFUART_MR1_PARITYMARK; in mcf_set_termios()
228 mr1 |= MCFUART_MR1_PARITYSPACE; in mcf_set_termios()
231 mr1 |= MCFUART_MR1_PARITYODD; in mcf_set_termios()
233 mr1 |= MCFUART_MR1_PARITYEVEN; in mcf_set_termios()
[all …]
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| H A D | mpc52xx_uart.c | 115 void (*set_mode)(struct uart_port *port, u8 mr1, u8 mr2);
148 static void mpc52xx_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) in mpc52xx_psc_set_mode() argument
151 out_8(&PSC(port)->mode, mr1); in mpc52xx_psc_set_mode()
922 static void mpc5125_psc_set_mode(struct uart_port *port, u8 mr1, u8 mr2) in mpc5125_psc_set_mode() argument
924 out_8(&PSC_5125(port)->mr1, mr1); in mpc5125_psc_set_mode()
961 return in_8(&PSC_5125(port)->mr1); in mpc5125_psc_get_mr1()
1173 unsigned char mr1, mr2; in mpc52xx_uart_set_termios() local
1178 mr1 = 0; in mpc52xx_uart_set_termios()
1181 case CS5: mr1 |= MPC52xx_PSC_MODE_5_BITS; in mpc52xx_uart_set_termios()
1183 case CS6: mr1 |= MPC52xx_PSC_MODE_6_BITS; in mpc52xx_uart_set_termios()
[all …]
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| H A D | sccnxp.c | 642 u8 mr1, mr2; in sccnxp_set_termios() local
660 mr1 = MR1_BITS_5; in sccnxp_set_termios()
663 mr1 = MR1_BITS_6; in sccnxp_set_termios()
666 mr1 = MR1_BITS_7; in sccnxp_set_termios()
670 mr1 = MR1_BITS_8; in sccnxp_set_termios()
677 mr1 |= MR1_PAR_ODD; in sccnxp_set_termios()
679 mr1 |= MR1_PAR_NO; in sccnxp_set_termios()
686 sccnxp_port_write(port, SCCNXP_MR_REG, mr1); in sccnxp_set_termios()
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| /openbmc/linux/drivers/ipack/devices/ |
| H A D | ipoctal.c | 502 unsigned char mr1 = 0; in ipoctal_set_termios() local
516 mr1 |= MR1_CHRL_6_BITS; in ipoctal_set_termios()
519 mr1 |= MR1_CHRL_7_BITS; in ipoctal_set_termios()
523 mr1 |= MR1_CHRL_8_BITS; in ipoctal_set_termios()
532 mr1 |= MR1_PARITY_ON | MR1_PARITY_ODD; in ipoctal_set_termios()
534 mr1 |= MR1_PARITY_ON | MR1_PARITY_EVEN; in ipoctal_set_termios()
536 mr1 |= MR1_PARITY_OFF; in ipoctal_set_termios()
551 mr1 |= MR1_RxRTS_CONTROL_ON; in ipoctal_set_termios()
554 mr1 |= MR1_RxRTS_CONTROL_OFF; in ipoctal_set_termios()
559 mr1 |= MR1_RxRTS_CONTROL_OFF; in ipoctal_set_termios()
[all …]
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| /openbmc/u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_k2g.c | 31 .mr1 = 0x00000006ul,
71 .mr1 = 0x00000006ul,
132 .mr1 = 0x00000006ul,
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| H A D | ddr3_cfg.c | 29 .mr1 = 0x00000006ul,
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| /openbmc/u-boot/board/imgtec/ci20/ |
| H A D | ci20.c | 288 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
290 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
332 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS | DDR3_MR1_DLL_DISABLE),
334 .mr1 = (DDR3_MR1_DIC_7 | DDR3_MR1_RTT_DIS),
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| /openbmc/u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a23.c | 38 .mr1 = 4,
115 writel(dram_para.mr1, &mctl_phy->mr1); in mctl_init()
200 writel((dram_para.mr0 << 16) | dram_para.mr1, &mctl_ctl->init3); in mctl_init()
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| H A D | dram_sun8i_a83t.c | 135 writel(MCTL_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
140 writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
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| H A D | dram_sun8i_a33.c | 134 writel(MCTL_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
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| /openbmc/qemu/tests/qtest/fuzz/ |
| H A D | generic_fuzz.c | 239 MemoryRegion *mr1; in fuzz_dma_read_cb() local
242 mr1 = address_space_translate(first_cpu->as, in fuzz_dma_read_cb()
252 if (!memory_region_is_ram(mr1)) { in fuzz_dma_read_cb()
253 l = fuzz_memory_access_size(mr1, l, addr1); in fuzz_dma_read_cb()
255 if (memory_region_is_ram(mr1) || in fuzz_dma_read_cb()
256 memory_region_is_romd(mr1) || in fuzz_dma_read_cb()
257 mr1 == sparse_mem_mr) { in fuzz_dma_read_cb()
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| /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 29 unsigned int mr1; member
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| /openbmc/u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 25 u32 mr1; member
185 u32 mr1; /* 0x58 mode register 1 */ member
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| H A D | dram_sun8i_a33.h | 75 u32 mr1; /* 0x34 */ member
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| H A D | dram_sun8i_a83t.h | 75 u32 mr1; /* 0x34 */ member
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| H A D | dram_sun9i.h | 108 u32 mr1; /* 0xa0 mode register 1 */ member
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| H A D | dram_sun6i.h | 174 u32 mr1; /* 0x44 mode register 1 */ member
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| /openbmc/linux/drivers/net/ethernet/ibm/emac/ |
| H A D | core.c | 580 u32 r, mr1 = 0; in emac_configure() local
585 out_be32(&p->mr1, in_be32(&p->mr1) in emac_configure()
603 mr1 = EMAC_MR1_FDE | EMAC_MR1_ILE; in emac_configure()
607 mr1 |= EMAC_MR1_FDE | EMAC_MR1_MWSW_001; in emac_configure()
614 mr1 |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_MF_IPPA( in emac_configure()
623 mr1 |= EMAC_MR1_MF_1000; in emac_configure()
631 mr1 |= EMAC4_MR1_JPSM; in emac_configure()
633 mr1 |= EMAC_MR1_JPSM; in emac_configure()
639 mr1 |= EMAC_MR1_MF_100; in emac_configure()
658 mr1 |= EMAC_MR1_EIFC | EMAC_MR1_APP; in emac_configure()
[all …]
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| H A D | emac.h | 30 u32 mr1; /* Reset */ member
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| /openbmc/u-boot/drivers/ram/stm32mp1/ |
| H A D | stm32mp1_ddr.h | 138 u32 mr1; member
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| /openbmc/u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 35 debug_ddr_cfg("mr1 0x%08X\n", ptr->mr1); in dump_phy_config()
350 spd_cb->phy_cfg.mr1 = 0 << 12 | 0 << 11 | 0 << 7 | 0 << 3 | in init_ddr3param()
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| /openbmc/u-boot/arch/arm/mach-omap2/omap4/ |
| H A D | sdram_elpida.c | 308 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
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| /openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | sdram.c | 75 writel(ddr_config->mr1, ddr_phy_regs + DDRP_MR1); in ddr_phy_init()
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| /openbmc/linux/arch/powerpc/include/asm/ |
| H A D | mpc52xx_psc.h | 304 u8 mr1; /* PSC + 0x00 */ member
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| /openbmc/u-boot/arch/arm/mach-omap2/omap5/ |
| H A D | sdram.c | 440 .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
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