xref: /openbmc/u-boot/arch/arm/mach-keystone/include/mach/ddr3.h (revision 83d290c56fab2d38cd1ab4c4cc7099559c1d5046)
1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */
2dc7de222SMasahiro Yamada /*
3dc7de222SMasahiro Yamada  * DDR3
4dc7de222SMasahiro Yamada  *
5dc7de222SMasahiro Yamada  * (C) Copyright 2014
6dc7de222SMasahiro Yamada  *     Texas Instruments Incorporated, <www.ti.com>
7dc7de222SMasahiro Yamada  */
8dc7de222SMasahiro Yamada 
9dc7de222SMasahiro Yamada #ifndef _DDR3_H_
10dc7de222SMasahiro Yamada #define _DDR3_H_
11dc7de222SMasahiro Yamada 
12dc7de222SMasahiro Yamada #include <asm/arch/hardware.h>
13dc7de222SMasahiro Yamada 
14dc7de222SMasahiro Yamada struct ddr3_phy_config {
15dc7de222SMasahiro Yamada 	unsigned int pllcr;
16dc7de222SMasahiro Yamada 	unsigned int pgcr1_mask;
17dc7de222SMasahiro Yamada 	unsigned int pgcr1_val;
18dc7de222SMasahiro Yamada 	unsigned int ptr0;
19dc7de222SMasahiro Yamada 	unsigned int ptr1;
20dc7de222SMasahiro Yamada 	unsigned int ptr2;
21dc7de222SMasahiro Yamada 	unsigned int ptr3;
22dc7de222SMasahiro Yamada 	unsigned int ptr4;
23dc7de222SMasahiro Yamada 	unsigned int dcr_mask;
24dc7de222SMasahiro Yamada 	unsigned int dcr_val;
25dc7de222SMasahiro Yamada 	unsigned int dtpr0;
26dc7de222SMasahiro Yamada 	unsigned int dtpr1;
27dc7de222SMasahiro Yamada 	unsigned int dtpr2;
28dc7de222SMasahiro Yamada 	unsigned int mr0;
29dc7de222SMasahiro Yamada 	unsigned int mr1;
30dc7de222SMasahiro Yamada 	unsigned int mr2;
31dc7de222SMasahiro Yamada 	unsigned int dtcr;
32dc7de222SMasahiro Yamada 	unsigned int pgcr2;
33dc7de222SMasahiro Yamada 	unsigned int zq0cr1;
34dc7de222SMasahiro Yamada 	unsigned int zq1cr1;
35dc7de222SMasahiro Yamada 	unsigned int zq2cr1;
36dc7de222SMasahiro Yamada 	unsigned int pir_v1;
37f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_2_mask;
38f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_2_val;
39f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_3_mask;
40f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_3_val;
41f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_4_mask;
42f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_4_val;
43f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_5_mask;
44f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_5_val;
45f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_6_mask;
46f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_6_val;
47f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_7_mask;
48f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_7_val;
49f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_8_mask;
50f8b4a2d7SCooper Jr., Franklin 	unsigned int datx8_8_val;
51dc7de222SMasahiro Yamada 	unsigned int pir_v2;
52dc7de222SMasahiro Yamada };
53dc7de222SMasahiro Yamada 
54dc7de222SMasahiro Yamada struct ddr3_emif_config {
55dc7de222SMasahiro Yamada 	unsigned int sdcfg;
56dc7de222SMasahiro Yamada 	unsigned int sdtim1;
57dc7de222SMasahiro Yamada 	unsigned int sdtim2;
58dc7de222SMasahiro Yamada 	unsigned int sdtim3;
59dc7de222SMasahiro Yamada 	unsigned int sdtim4;
60dc7de222SMasahiro Yamada 	unsigned int zqcfg;
61dc7de222SMasahiro Yamada 	unsigned int sdrfc;
62dc7de222SMasahiro Yamada };
63dc7de222SMasahiro Yamada 
64d9a76e77SVitaly Andrianov struct ddr3_spd_cb {
65d9a76e77SVitaly Andrianov 	char   dimm_name[32];
66d9a76e77SVitaly Andrianov 	struct ddr3_phy_config phy_cfg;
67d9a76e77SVitaly Andrianov 	struct ddr3_emif_config emif_cfg;
68d9a76e77SVitaly Andrianov 	unsigned int ddrspdclock;
69d9a76e77SVitaly Andrianov 	int    ddr_size_gbyte;
70d9a76e77SVitaly Andrianov };
71d9a76e77SVitaly Andrianov 
72dc7de222SMasahiro Yamada u32 ddr3_init(void);
73dc7de222SMasahiro Yamada void ddr3_reset_ddrphy(void);
74dc7de222SMasahiro Yamada void ddr3_init_ecc(u32 base, u32 ddr3_size);
75dc7de222SMasahiro Yamada void ddr3_disable_ecc(u32 base);
76dc7de222SMasahiro Yamada void ddr3_check_ecc_int(u32 base);
77dc7de222SMasahiro Yamada int ddr3_ecc_support_rmw(u32 base);
78dc7de222SMasahiro Yamada void ddr3_err_reset_workaround(void);
79dc7de222SMasahiro Yamada void ddr3_enable_ecc(u32 base, int test);
80dc7de222SMasahiro Yamada void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
81dc7de222SMasahiro Yamada void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
828efc2437SVitaly Andrianov int ddr3_get_size(void);
83dc7de222SMasahiro Yamada 
84dc7de222SMasahiro Yamada #endif
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