Searched refs:mpuclk (Results 1 – 9 of 9) sorted by relevance
24 u32 mpuclk; member132 { "mpuclk", offsetof(struct mainpll_cfg, mpuclk) },307 clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) in cm_calc_handoff_mpu_clk_hz()312 clk_hz /= ((main_cfg->mpuclk >> in cm_calc_handoff_mpu_clk_hz()445 clk = main_cfg->mpuclk; in cm_calculate_numer()457 clk = main_cfg->mpuclk; in cm_calculate_numer()746 writel(main_cfg->mpuclk, in cm_full_cfg()807 &clock_manager_base->main_pll.mpuclk); in cm_full_cfg()
147 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()150 writel(cfg->altera_grp_mpuclk, &clock_manager_base->altera.mpuclk); in cm_basic_init()365 reg = readl(&clock_manager_base->altera.mpuclk); in cm_get_mpu_clk_hz()367 reg = readl(&clock_manager_base->main_pll.mpuclk); in cm_get_mpu_clk_hz()
118 writel(0xff, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()137 writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk); in cm_basic_init()237 unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk); in cm_get_mpu_clk_hz()267 clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) & in cm_get_mpu_clk_hz()
14 u32 mpuclk; member51 u32 mpuclk; member95 u32 mpuclk; member
20 u32 mpuclk; member65 u32 mpuclk; member
79 u32 mpuclk; member
76 mpuclk-cnt = <0>; /* Field: mpuclk.cnt */77 mpuclk-src = <0>; /* Field: mpuclk.src */129 mpuclk = <0x03840001>; /* Register: mpuclk */
150 mpuclk: mpuclk@48 { label287 clocks = <&mpuclk>;294 clocks = <&mpuclk>;
152 mpuclk: mpuclk@48 { label289 clocks = <&mpuclk>;296 clocks = <&mpuclk>;