Searched refs:mideleg (Results 1 – 6 of 6) sorted by relevance
470 uint64_t irqs = riscv_cpu_all_pending(env) & ~env->mideleg & in riscv_cpu_mirq_pending()479 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & in riscv_cpu_sirq_pending()481 uint64_t irqs_f = env->mvip & env->mvien & ~env->mideleg & env->sie; in riscv_cpu_sirq_pending()489 uint64_t irqs = riscv_cpu_all_pending(env) & env->mideleg & env->hideleg; in riscv_cpu_vsirq_pending()526 irqs = pending & ~env->mideleg & -mie; in riscv_cpu_local_irq_pending()533 irqs_f = env->mvip & (env->mvien & ~env->mideleg) & env->sie; in riscv_cpu_local_irq_pending()536 irqs = ((pending & env->mideleg & ~env->hideleg) | irqs_f) & -hsie; in riscv_cpu_local_irq_pending()546 irq_delegated = pending & env->mideleg & env->hideleg; in riscv_cpu_local_irq_pending()1804 uint64_t deleg = async ? env->mideleg : env->medeleg; in riscv_cpu_do_interrupt()
1788 *ret_val = env->mideleg; in rmw_mideleg64()1791 env->mideleg = (env->mideleg & ~mask) | (new_val & mask); in rmw_mideleg64()1794 env->mideleg |= HS_MODE_INTERRUPTS; in rmw_mideleg64()2858 (env->mideleg | ~env->mvien)) | MIP_STIP; in rmw_mvip64()2860 (~env->mideleg & env->mvien); in rmw_mvip64()2875 alias_mask &= (env->mideleg | env->mvien); in rmw_mvip64()2876 nalias_mask &= (env->mideleg | env->mvien); in rmw_mvip64()3086 (~env->mideleg & env->mvien); in rmw_sie64()3087 uint64_t alias_mask = (S_MODE_INTERRUPTS | LOCAL_INTERRUPTS) & env->mideleg; in rmw_sie64()3332 uint64_t mask = (env->mideleg | env->mvien) & sip_writable_mask; in rmw_sip64()[all …]
422 VMSTATE_UINT64(env.mideleg, RISCVCPU),
281 uint64_t mideleg; member
996 env->mideleg |= HS_MODE_INTERRUPTS; in riscv_cpu_reset_hold()
1007 env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP; in riscv_tcg_cpu_realize()