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Searched refs:mfspr (Results 1 – 25 of 277) sorted by relevance

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/openbmc/u-boot/arch/powerpc/lib/
H A Dbat_rw.c129 l = mfspr (DBAT0L); in read_bat()
130 u = mfspr (DBAT0U); in read_bat()
133 l = mfspr (IBAT0L); in read_bat()
134 u = mfspr (IBAT0U); in read_bat()
137 l = mfspr (DBAT1L); in read_bat()
138 u = mfspr (DBAT1U); in read_bat()
141 l = mfspr (IBAT1L); in read_bat()
142 u = mfspr (IBAT1U); in read_bat()
145 l = mfspr (DBAT2L); in read_bat()
146 u = mfspr (DBAT2U); in read_bat()
[all …]
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_hv_p9_perf.c49 host_os_sprs->mmcr0 = mfspr(SPRN_MMCR0); in switch_pmu_to_guest()
50 host_os_sprs->mmcra = mfspr(SPRN_MMCRA); in switch_pmu_to_guest()
54 host_os_sprs->pmc1 = mfspr(SPRN_PMC1); in switch_pmu_to_guest()
55 host_os_sprs->pmc2 = mfspr(SPRN_PMC2); in switch_pmu_to_guest()
56 host_os_sprs->pmc3 = mfspr(SPRN_PMC3); in switch_pmu_to_guest()
57 host_os_sprs->pmc4 = mfspr(SPRN_PMC4); in switch_pmu_to_guest()
58 host_os_sprs->pmc5 = mfspr(SPRN_PMC5); in switch_pmu_to_guest()
59 host_os_sprs->pmc6 = mfspr(SPRN_PMC6); in switch_pmu_to_guest()
60 host_os_sprs->mmcr1 = mfspr(SPRN_MMCR1); in switch_pmu_to_guest()
61 host_os_sprs->mmcr2 = mfspr(SPRN_MMCR2); in switch_pmu_to_guest()
[all …]
H A Dbook3s_hv_interrupts.S47 mfspr r3, SPRN_DSCR
52 mfspr r3, SPRN_DABR
71 mfspr r8,SPRN_DEC
116 mfspr r8, SPRN_MMCR2
122 mfspr r7, SPRN_MMCR0 /* save MMCR0 */
124 mfspr r6, SPRN_MMCRA
132 mfspr r5, SPRN_MMCR1
133 mfspr r9, SPRN_SIAR
134 mfspr r10, SPRN_SDAR
141 mfspr r9, SPRN_SIER
[all …]
H A Dbook3s_hv_p9_entry.c60 vcpu->arch.tar = mfspr(SPRN_TAR); in store_spr_state()
64 vcpu->arch.vrsave = mfspr(SPRN_VRSAVE); in store_spr_state()
68 vcpu->arch.ebbhr = mfspr(SPRN_EBBHR); in store_spr_state()
69 vcpu->arch.ebbrr = mfspr(SPRN_EBBRR); in store_spr_state()
70 vcpu->arch.bescr = mfspr(SPRN_BESCR); in store_spr_state()
74 vcpu->arch.tid = mfspr(SPRN_TIDR); in store_spr_state()
75 vcpu->arch.iamr = mfspr(SPRN_IAMR); in store_spr_state()
76 vcpu->arch.amr = mfspr(SPRN_AMR); in store_spr_state()
77 vcpu->arch.uamor = mfspr(SPRN_UAMOR); in store_spr_state()
78 vcpu->arch.fscr = mfspr(SPRN_FSCR); in store_spr_state()
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Dcpu_setup_ppc970.S25 mfspr r3,SPRN_HID4
32 mfspr r3,SPRN_HID5
40 mfspr r0,SPRN_HID1
76 mfspr r0,SPRN_HID0
90 mfspr r0,SPRN_HID0
98 mfspr r0,SPRN_HID0
99 mfspr r0,SPRN_HID0
100 mfspr r0,SPRN_HID0
101 mfspr r0,SPRN_HID0
102 mfspr r0,SPRN_HID0
[all …]
H A Dhead_booke.h50 mfspr r10, SPRN_SPRG_THREAD; \
54 mfspr r11, SPRN_SRR1; \
69 mfspr r13, SPRN_SPRG_RSCRATCH0; \
76 mfspr r12,SPRN_SRR0; \
78 mfspr r9,SPRN_SRR1; \
97 mfspr r2,SPRN_SPRG_THREAD
100 mfspr r10,SPRN_XER
116 mfspr r10, SPRN_SPRG_THREAD
123 mfspr r11, SPRN_SRR1
136 mfspr r9, SPRN_SRR1
[all …]
H A Dhead_44x.S311 mfspr r10, SPRN_DEAR /* Get faulting address */
322 mfspr r12,SPRN_MMUCR
329 mfspr r11,SPRN_SPRG_THREAD
333 mfspr r12,SPRN_MMUCR
334 mfspr r13,SPRN_PID /* Get PID */
357 mfspr r12,SPRN_ESR
395 mfspr r10,SPRN_DEAR
404 mfspr r11, SPRN_SPRG_RSCRATCH4
406 mfspr r13, SPRN_SPRG_RSCRATCH3
407 mfspr r12, SPRN_SPRG_RSCRATCH2
[all …]
H A Dhead_32.h22 mfspr r10, SPRN_SPRG_THREAD
25 mfspr r11, SPRN_DEAR
27 mfspr r11, SPRN_DAR
31 mfspr r11, SPRN_ESR
33 mfspr r11, SPRN_DSISR
37 mfspr r11, SPRN_SRR0
39 mfspr r11, SPRN_SRR1 /* check whether user or kernel */
49 mfspr r1,SPRN_SPRG_THREAD
71 mfspr r11, SPRN_SPRG_SCRATCH2
83 mfspr r10,SPRN_SPRG_SCRATCH0
[all …]
H A Dhead_40x.S112 mfspr r10,SPRN_SRR0
113 mfspr r11,SPRN_SRR1
116 mfspr r10,SPRN_DEAR
117 mfspr r11,SPRN_ESR
121 mfspr r11,SPRN_SRR3 /* check whether user or kernel */
127 mfspr r11,SPRN_SPRG_THREAD /* if from user, start at top of */
159 mfspr r12,SPRN_SRR2
160 mfspr r9,SPRN_SRR3
281 mfspr r9, SPRN_PID
283 mfspr r10, SPRN_DEAR /* Get faulting address */
[all …]
H A D85xx_entry_mapping.S8 mfspr r7, SPRN_PID0
13 mfspr r7,SPRN_MAS1
17 mfspr r7,SPRN_MMUCFG
22 mfspr r7,SPRN_PID1
27 mfspr r7,SPRN_MAS1
30 mfspr r7, SPRN_PID2
37 mfspr r7,SPRN_MAS0
40 mfspr r7,SPRN_MAS1 /* Insure IPROT set */
46 mfspr r9,SPRN_TLB1CFG
53 mfspr r7,SPRN_MAS1
[all …]
H A Dcpu_setup_e500.S22 mfspr r0, SPRN_L1CSR1
32 mfspr r0, SPRN_L1CSR0
44 1: mfspr r0, SPRN_L1CSR0
61 mfspr r3, SPRN_PWRMGTCR0
80 mfspr r3, SPRN_PWRMGTCR0
99 mfspr r10,SPRN_MMUCFG
123 mfspr r3,SPRN_HID1
141 mfspr r3, SPRN_MMUCFG
169 mfspr r10,SPRN_MMUCFG
192 mfspr r10,SPRN_MMUCFG
[all …]
H A Dcpu_setup_power.c64 fscr = mfspr(SPRN_FSCR); in init_FSCR()
73 fscr = mfspr(SPRN_FSCR); in init_FSCR_power9()
83 fscr = mfspr(SPRN_FSCR); in init_FSCR_power10()
93 hfscr = mfspr(SPRN_HFSCR); in init_HFSCR()
148 init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH); in __setup_cpu_power7()
162 init_LPCR_ISA206(mfspr(SPRN_LPCR), LPCR_LPES1 >> LPCR_LPES_SH); in __restore_cpu_power7()
177 init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */ in __setup_cpu_power8()
198 init_LPCR_ISA206(mfspr(SPRN_LPCR) | LPCR_PECEDH, 0); /* LPES = 0 */ in __restore_cpu_power8()
217 init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\ in __setup_cpu_power9()
239 init_LPCR_ISA300((mfspr(SPRN_LPCR) | LPCR_PECEDH | LPCR_PECE_HVEE |\ in __restore_cpu_power9()
[all …]
H A Dexceptions-64e.S85 mfspr r10,SPRN_SPRG_TLB_EXFRAME
93 mfspr r10,SPRN_SRR0
95 mfspr r10,SPRN_SRR1
97 mfspr r10,SPRN_SPRG_GEN_SCRATCH
99 mfspr r10,SPRN_SPRG_TLB_SCRATCH
101 mfspr r10,SPRN_MAS0
103 mfspr r10,SPRN_MAS1
105 mfspr r10,SPRN_MAS2
107 mfspr r10,SPRN_MAS3
109 mfspr r10,SPRN_MAS6
[all …]
H A Dcpu_setup_6xx.S96 mfspr r11,SPRN_HID0
115 mfspr r11,SPRN_HID0
129 mfspr r11,SPRN_HID2_G2_LE
164 mfspr r11,SPRN_MSSSR0
187 mfspr r11,SPRN_HID0
212 mfspr r10, SPRN_HID1
249 mfspr r11,SPRN_L3CR
260 mfspr r11,SPRN_HID0
291 mfspr r3,SPRN_L2CR
294 mfspr r3,SPRN_MSSCR0
[all …]
H A Dswsusp_85xx.S65 mfspr r4,SPRN_TCR
69 1: mfspr r4,SPRN_TBRU
71 mfspr r5,SPRN_TBRL
73 mfspr r3,SPRN_TBRU
78 mfspr r4,SPRN_SPRG0
80 mfspr r4,SPRN_SPRG1
82 mfspr r4,SPRN_SPRG2
84 mfspr r4,SPRN_SPRG3
86 mfspr r4,SPRN_SPRG4
88 mfspr r4,SPRN_SPRG5
[all …]
H A Dhead_8xx.S199 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
206 mfspr r10, SPRN_M_TWB /* Get level 1 table */
216 mfspr r10, SPRN_MD_TWC
233 0: mfspr r10, SPRN_SPRG_SCRATCH2
234 mfspr r11, SPRN_M_TW
243 mfspr r10, SPRN_SPRG_SCRATCH2
244 mfspr r11, SPRN_M_TW
256 mfspr r10, SPRN_MD_EPN
258 mfspr r10, SPRN_M_TWB /* Get level 1 table */
267 mfspr r10, SPRN_MD_TWC
[all …]
/openbmc/linux/arch/powerpc/platforms/83xx/
H A Dsuspend-asm.S69 mfspr r5, SPRN_HID0
70 mfspr r6, SPRN_HID1
71 mfspr r7, SPRN_HID2
77 mfspr r4, SPRN_IABR
78 mfspr r5, SPRN_IABR2
79 mfspr r6, SPRN_IBCR
80 mfspr r7, SPRN_DABR
81 mfspr r8, SPRN_DABR2
82 mfspr r9, SPRN_DBCR
91 mfspr r4, SPRN_SPRG0
[all …]
/openbmc/linux/tools/testing/selftests/powerpc/pmu/ebb/
H A Debb.c39 val = mfspr(SPRN_MMCR0); in reset_ebb_with_clear_mask()
61 val = mfspr(SPRN_MMCR0); in ebb_check_mmcr0()
104 val = mfspr(SPRN_BESCR); in standard_ebb_callee()
113 val = mfspr(SPRN_MMCR0); in standard_ebb_callee()
221 mmcr0 = mfspr(SPRN_MMCR0); in dump_ebb_hw_state()
222 bescr = mfspr(SPRN_BESCR); in dump_ebb_hw_state()
236 mmcr0, decode_mmcr0(mmcr0), mfspr(SPRN_MMCR2), in dump_ebb_hw_state()
237 mfspr(SPRN_EBBHR), bescr, decode_bescr(bescr), in dump_ebb_hw_state()
238 mfspr(SPRN_PMC1), mfspr(SPRN_PMC2), mfspr(SPRN_PMC3), in dump_ebb_hw_state()
239 mfspr(SPRN_PMC4), mfspr(SPRN_PMC5), mfspr(SPRN_PMC6), in dump_ebb_hw_state()
[all …]
/openbmc/linux/arch/openrisc/kernel/
H A Dsetup.c98 unsigned long upr = mfspr(SPR_UPR); in print_cpuinfo()
99 unsigned long vr = mfspr(SPR_VR); in print_cpuinfo()
133 1 << ((mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTS) >> 2), in print_cpuinfo()
134 1 + (mfspr(SPR_DMMUCFGR) & SPR_DMMUCFGR_NTW)); in print_cpuinfo()
137 1 << ((mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTS) >> 2), in print_cpuinfo()
138 1 + (mfspr(SPR_IMMUCFGR) & SPR_IMMUCFGR_NTW)); in print_cpuinfo()
167 iccfgr = mfspr(SPR_ICCFGR); in setup_cpuinfo()
174 dccfgr = mfspr(SPR_DCCFGR); in setup_cpuinfo()
189 cpuinfo->coreid = mfspr(SPR_COREID); in setup_cpuinfo()
299 vr = mfspr(SPR_VR); in show_cpuinfo()
[all …]
H A Dhead.S55 #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
58 #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
64 #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
67 #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
70 #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
98 #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
101 #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
104 #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
107 #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
[all …]
/openbmc/linux/arch/powerpc/platforms/powernv/
H A Didle.c74 uint64_t lpcr_val = mfspr(SPRN_LPCR); in pnv_save_sprs_for_deep_states()
75 uint64_t hid0_val = mfspr(SPRN_HID0); in pnv_save_sprs_for_deep_states()
76 uint64_t hmeer_val = mfspr(SPRN_HMEER); in pnv_save_sprs_for_deep_states()
117 uint64_t hid1_val = mfspr(SPRN_HID1); in pnv_save_sprs_for_deep_states()
118 uint64_t hid4_val = mfspr(SPRN_HID4); in pnv_save_sprs_for_deep_states()
119 uint64_t hid5_val = mfspr(SPRN_HID5); in pnv_save_sprs_for_deep_states()
343 sprs.tscr = mfspr(SPRN_TSCR); in power7_idle_insn()
344 sprs.worc = mfspr(SPRN_WORC); in power7_idle_insn()
346 sprs.sdr1 = mfspr(SPRN_SDR1); in power7_idle_insn()
347 sprs.rpr = mfspr(SPRN_RPR); in power7_idle_insn()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Drelease.S32 mfspr r3, SPRN_HDBCR0
48 mfspr r0,PVR
59 mfspr r3,SPRN_HDBCR1
65 mfspr r3,SPRN_SVR
83 mfspr r3,SPRN_HDBCR0
106 mfspr r3,SPRN_L1CSR1
115 mfspr r3,SPRN_L1CSR1
124 mfspr r3,SPRN_L1CSR0
133 mfspr r3,SPRN_L1CSR0
144 mfspr r0,SPRN_PIR
[all …]
H A Dtlb.c52 _mas1 = mfspr(MAS1); in read_tlbcam_entry()
56 *epn = mfspr(MAS2) & MAS2_EPN; in read_tlbcam_entry()
57 *rpn = mfspr(MAS3) & MAS3_RPN; in read_tlbcam_entry()
59 *rpn |= ((u64)mfspr(MAS7)) << 32; in read_tlbcam_entry()
66 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in print_tlbcam()
102 unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff; in init_used_tlb_cams()
111 if (mfspr(MAS1) & MAS1_VALID) in init_used_tlb_cams()
145 if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 && in set_tlb()
207 _mas0 = mfspr(MAS0); in find_tlb_idx()
208 _mas1 = mfspr(MAS1); in find_tlb_idx()
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc86xx/
H A Drelease.S30 mfspr r0, MSSCR0
58 mfspr r0, HID0
75 mfspr r3, l2cr
79 mfspr r3, l2cr
88 1: mfspr r3, l2cr
93 mfspr r3, l2cr
100 mfspr r3, HID0
119 mfspr r3, HID0
130 mfspr r4, HID0
137 mfspr r4, HID1
/openbmc/linux/arch/powerpc/platforms/powermac/
H A Dcache.S56 mfspr r8,SPRN_HID0 /* Save SPRN_HID0 in r8 */
85 mfspr r3,SPRN_HID0
99 mfspr r5,SPRN_L2CR
156 1: mfspr r3,SPRN_L2CR
167 mfspr r0,SPRN_HID0
175 mfspr r0,SPRN_HID0
204 mfspr r0,SPRN_MSSCR0
246 mfspr r6,SPRN_LDSTCR
271 mfspr r3,SPRN_L2CR
291 3: mfspr r0,SPRN_L2CR /* wait for it to go to 0 */
[all …]

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