1d2912cb1SThomas Gleixner/* SPDX-License-Identifier: GPL-2.0-only */ 2d49747bdSScott Wood/* 3d49747bdSScott Wood * Enter and leave deep sleep state on MPC83xx 4d49747bdSScott Wood * 5d49747bdSScott Wood * Copyright (c) 2006-2008 Freescale Semiconductor, Inc. 6d49747bdSScott Wood * Author: Scott Wood <scottwood@freescale.com> 7d49747bdSScott Wood */ 8d49747bdSScott Wood 9d49747bdSScott Wood#include <asm/page.h> 10d49747bdSScott Wood#include <asm/ppc_asm.h> 11d49747bdSScott Wood#include <asm/reg.h> 12d49747bdSScott Wood#include <asm/asm-offsets.h> 13d49747bdSScott Wood 14d49747bdSScott Wood#define SS_MEMSAVE 0x00 /* First 8 bytes of RAM */ 15d49747bdSScott Wood#define SS_HID 0x08 /* 3 HIDs */ 16d49747bdSScott Wood#define SS_IABR 0x14 /* 2 IABRs */ 17d49747bdSScott Wood#define SS_IBCR 0x1c 18d49747bdSScott Wood#define SS_DABR 0x20 /* 2 DABRs */ 19d49747bdSScott Wood#define SS_DBCR 0x28 20d49747bdSScott Wood#define SS_SP 0x2c 21d49747bdSScott Wood#define SS_SR 0x30 /* 16 segment registers */ 22d49747bdSScott Wood#define SS_R2 0x70 23d49747bdSScott Wood#define SS_MSR 0x74 24d49747bdSScott Wood#define SS_SDR1 0x78 25d49747bdSScott Wood#define SS_LR 0x7c 2636da5ff0SChristophe Leroy#define SS_SPRG 0x80 /* 8 SPRGs */ 2736da5ff0SChristophe Leroy#define SS_DBAT 0xa0 /* 8 DBATs */ 2836da5ff0SChristophe Leroy#define SS_IBAT 0xe0 /* 8 IBATs */ 2936da5ff0SChristophe Leroy#define SS_TB 0x120 3036da5ff0SChristophe Leroy#define SS_CR 0x128 3136da5ff0SChristophe Leroy#define SS_GPREG 0x12c /* r12-r31 */ 3236da5ff0SChristophe Leroy#define STATE_SAVE_SIZE 0x17c 33d49747bdSScott Wood 34d49747bdSScott Wood .section .data 35d49747bdSScott Wood .align 5 36d49747bdSScott Wood 37d49747bdSScott Woodmpc83xx_sleep_save_area: 38d49747bdSScott Wood .space STATE_SAVE_SIZE 39d49747bdSScott Woodimmrbase: 40d49747bdSScott Wood .long 0 41d49747bdSScott Wood 42d49747bdSScott Wood .section .text 43d49747bdSScott Wood .align 5 44d49747bdSScott Wood 45d49747bdSScott Wood /* r3 = physical address of IMMR */ 46d49747bdSScott Wood_GLOBAL(mpc83xx_enter_deep_sleep) 47d49747bdSScott Wood lis r4, immrbase@ha 48d49747bdSScott Wood stw r3, immrbase@l(r4) 49d49747bdSScott Wood 50d49747bdSScott Wood /* The first 2 words of memory are used to communicate with the 51d49747bdSScott Wood * bootloader, to tell it how to resume. 52d49747bdSScott Wood * 53d49747bdSScott Wood * The first word is the magic number 0xf5153ae5, and the second 54d49747bdSScott Wood * is the pointer to mpc83xx_deep_resume. 55d49747bdSScott Wood * 56d49747bdSScott Wood * The original content of these two words is saved in SS_MEMSAVE. 57d49747bdSScott Wood */ 58d49747bdSScott Wood 59d49747bdSScott Wood lis r3, mpc83xx_sleep_save_area@h 60d49747bdSScott Wood ori r3, r3, mpc83xx_sleep_save_area@l 61d49747bdSScott Wood 62d49747bdSScott Wood lis r4, KERNELBASE@h 63d49747bdSScott Wood lwz r5, 0(r4) 64d49747bdSScott Wood lwz r6, 4(r4) 65d49747bdSScott Wood 66d49747bdSScott Wood stw r5, SS_MEMSAVE+0(r3) 67d49747bdSScott Wood stw r6, SS_MEMSAVE+4(r3) 68d49747bdSScott Wood 69d49747bdSScott Wood mfspr r5, SPRN_HID0 70d49747bdSScott Wood mfspr r6, SPRN_HID1 71d49747bdSScott Wood mfspr r7, SPRN_HID2 72d49747bdSScott Wood 73d49747bdSScott Wood stw r5, SS_HID+0(r3) 74d49747bdSScott Wood stw r6, SS_HID+4(r3) 75d49747bdSScott Wood stw r7, SS_HID+8(r3) 76d49747bdSScott Wood 77d49747bdSScott Wood mfspr r4, SPRN_IABR 78d49747bdSScott Wood mfspr r5, SPRN_IABR2 79d49747bdSScott Wood mfspr r6, SPRN_IBCR 80d49747bdSScott Wood mfspr r7, SPRN_DABR 81d49747bdSScott Wood mfspr r8, SPRN_DABR2 82d49747bdSScott Wood mfspr r9, SPRN_DBCR 83d49747bdSScott Wood 84d49747bdSScott Wood stw r4, SS_IABR+0(r3) 85d49747bdSScott Wood stw r5, SS_IABR+4(r3) 86d49747bdSScott Wood stw r6, SS_IBCR(r3) 87d49747bdSScott Wood stw r7, SS_DABR+0(r3) 88d49747bdSScott Wood stw r8, SS_DABR+4(r3) 89d49747bdSScott Wood stw r9, SS_DBCR(r3) 90d49747bdSScott Wood 91d49747bdSScott Wood mfspr r4, SPRN_SPRG0 92d49747bdSScott Wood mfspr r5, SPRN_SPRG1 93d49747bdSScott Wood mfspr r6, SPRN_SPRG2 94d49747bdSScott Wood mfspr r7, SPRN_SPRG3 95d49747bdSScott Wood mfsdr1 r8 96d49747bdSScott Wood 97d49747bdSScott Wood stw r4, SS_SPRG+0(r3) 98d49747bdSScott Wood stw r5, SS_SPRG+4(r3) 99d49747bdSScott Wood stw r6, SS_SPRG+8(r3) 100d49747bdSScott Wood stw r7, SS_SPRG+12(r3) 101d49747bdSScott Wood stw r8, SS_SDR1(r3) 102d49747bdSScott Wood 10336da5ff0SChristophe Leroy mfspr r4, SPRN_SPRG4 10436da5ff0SChristophe Leroy mfspr r5, SPRN_SPRG5 10536da5ff0SChristophe Leroy mfspr r6, SPRN_SPRG6 10636da5ff0SChristophe Leroy mfspr r7, SPRN_SPRG7 10736da5ff0SChristophe Leroy 10836da5ff0SChristophe Leroy stw r4, SS_SPRG+16(r3) 10936da5ff0SChristophe Leroy stw r5, SS_SPRG+20(r3) 11036da5ff0SChristophe Leroy stw r6, SS_SPRG+24(r3) 11136da5ff0SChristophe Leroy stw r7, SS_SPRG+28(r3) 11236da5ff0SChristophe Leroy 113d49747bdSScott Wood mfspr r4, SPRN_DBAT0U 114d49747bdSScott Wood mfspr r5, SPRN_DBAT0L 115d49747bdSScott Wood mfspr r6, SPRN_DBAT1U 116d49747bdSScott Wood mfspr r7, SPRN_DBAT1L 117d49747bdSScott Wood 118d49747bdSScott Wood stw r4, SS_DBAT+0x00(r3) 119d49747bdSScott Wood stw r5, SS_DBAT+0x04(r3) 120d49747bdSScott Wood stw r6, SS_DBAT+0x08(r3) 121d49747bdSScott Wood stw r7, SS_DBAT+0x0c(r3) 122d49747bdSScott Wood 123d49747bdSScott Wood mfspr r4, SPRN_DBAT2U 124d49747bdSScott Wood mfspr r5, SPRN_DBAT2L 125d49747bdSScott Wood mfspr r6, SPRN_DBAT3U 126d49747bdSScott Wood mfspr r7, SPRN_DBAT3L 127d49747bdSScott Wood 128d49747bdSScott Wood stw r4, SS_DBAT+0x10(r3) 129d49747bdSScott Wood stw r5, SS_DBAT+0x14(r3) 130d49747bdSScott Wood stw r6, SS_DBAT+0x18(r3) 131d49747bdSScott Wood stw r7, SS_DBAT+0x1c(r3) 132d49747bdSScott Wood 133d49747bdSScott Wood mfspr r4, SPRN_DBAT4U 134d49747bdSScott Wood mfspr r5, SPRN_DBAT4L 135d49747bdSScott Wood mfspr r6, SPRN_DBAT5U 136d49747bdSScott Wood mfspr r7, SPRN_DBAT5L 137d49747bdSScott Wood 138d49747bdSScott Wood stw r4, SS_DBAT+0x20(r3) 139d49747bdSScott Wood stw r5, SS_DBAT+0x24(r3) 140d49747bdSScott Wood stw r6, SS_DBAT+0x28(r3) 141d49747bdSScott Wood stw r7, SS_DBAT+0x2c(r3) 142d49747bdSScott Wood 143d49747bdSScott Wood mfspr r4, SPRN_DBAT6U 144d49747bdSScott Wood mfspr r5, SPRN_DBAT6L 145d49747bdSScott Wood mfspr r6, SPRN_DBAT7U 146d49747bdSScott Wood mfspr r7, SPRN_DBAT7L 147d49747bdSScott Wood 148d49747bdSScott Wood stw r4, SS_DBAT+0x30(r3) 149d49747bdSScott Wood stw r5, SS_DBAT+0x34(r3) 150d49747bdSScott Wood stw r6, SS_DBAT+0x38(r3) 151d49747bdSScott Wood stw r7, SS_DBAT+0x3c(r3) 152d49747bdSScott Wood 153d49747bdSScott Wood mfspr r4, SPRN_IBAT0U 154d49747bdSScott Wood mfspr r5, SPRN_IBAT0L 155d49747bdSScott Wood mfspr r6, SPRN_IBAT1U 156d49747bdSScott Wood mfspr r7, SPRN_IBAT1L 157d49747bdSScott Wood 158d49747bdSScott Wood stw r4, SS_IBAT+0x00(r3) 159d49747bdSScott Wood stw r5, SS_IBAT+0x04(r3) 160d49747bdSScott Wood stw r6, SS_IBAT+0x08(r3) 161d49747bdSScott Wood stw r7, SS_IBAT+0x0c(r3) 162d49747bdSScott Wood 163d49747bdSScott Wood mfspr r4, SPRN_IBAT2U 164d49747bdSScott Wood mfspr r5, SPRN_IBAT2L 165d49747bdSScott Wood mfspr r6, SPRN_IBAT3U 166d49747bdSScott Wood mfspr r7, SPRN_IBAT3L 167d49747bdSScott Wood 168d49747bdSScott Wood stw r4, SS_IBAT+0x10(r3) 169d49747bdSScott Wood stw r5, SS_IBAT+0x14(r3) 170d49747bdSScott Wood stw r6, SS_IBAT+0x18(r3) 171d49747bdSScott Wood stw r7, SS_IBAT+0x1c(r3) 172d49747bdSScott Wood 173d49747bdSScott Wood mfspr r4, SPRN_IBAT4U 174d49747bdSScott Wood mfspr r5, SPRN_IBAT4L 175d49747bdSScott Wood mfspr r6, SPRN_IBAT5U 176d49747bdSScott Wood mfspr r7, SPRN_IBAT5L 177d49747bdSScott Wood 178d49747bdSScott Wood stw r4, SS_IBAT+0x20(r3) 179d49747bdSScott Wood stw r5, SS_IBAT+0x24(r3) 180d49747bdSScott Wood stw r6, SS_IBAT+0x28(r3) 181d49747bdSScott Wood stw r7, SS_IBAT+0x2c(r3) 182d49747bdSScott Wood 183d49747bdSScott Wood mfspr r4, SPRN_IBAT6U 184d49747bdSScott Wood mfspr r5, SPRN_IBAT6L 185d49747bdSScott Wood mfspr r6, SPRN_IBAT7U 186d49747bdSScott Wood mfspr r7, SPRN_IBAT7L 187d49747bdSScott Wood 188d49747bdSScott Wood stw r4, SS_IBAT+0x30(r3) 189d49747bdSScott Wood stw r5, SS_IBAT+0x34(r3) 190d49747bdSScott Wood stw r6, SS_IBAT+0x38(r3) 191d49747bdSScott Wood stw r7, SS_IBAT+0x3c(r3) 192d49747bdSScott Wood 193d49747bdSScott Wood mfmsr r4 194d49747bdSScott Wood mflr r5 195d49747bdSScott Wood mfcr r6 196d49747bdSScott Wood 197d49747bdSScott Wood stw r4, SS_MSR(r3) 198d49747bdSScott Wood stw r5, SS_LR(r3) 199d49747bdSScott Wood stw r6, SS_CR(r3) 200d49747bdSScott Wood stw r1, SS_SP(r3) 201d49747bdSScott Wood stw r2, SS_R2(r3) 202d49747bdSScott Wood 203d49747bdSScott Wood1: mftbu r4 204d49747bdSScott Wood mftb r5 205d49747bdSScott Wood mftbu r6 206d49747bdSScott Wood cmpw r4, r6 207d49747bdSScott Wood bne 1b 208d49747bdSScott Wood 209d49747bdSScott Wood stw r4, SS_TB+0(r3) 210d49747bdSScott Wood stw r5, SS_TB+4(r3) 211d49747bdSScott Wood 212d49747bdSScott Wood stmw r12, SS_GPREG(r3) 213d49747bdSScott Wood 214d49747bdSScott Wood li r4, 0 215d49747bdSScott Wood addi r6, r3, SS_SR-4 216d49747bdSScott Wood1: mfsrin r5, r4 217d49747bdSScott Wood stwu r5, 4(r6) 218d49747bdSScott Wood addis r4, r4, 0x1000 219d49747bdSScott Wood cmpwi r4, 0 220d49747bdSScott Wood bne 1b 221d49747bdSScott Wood 222d49747bdSScott Wood /* Disable machine checks and critical exceptions */ 223d49747bdSScott Wood mfmsr r4 224d49747bdSScott Wood rlwinm r4, r4, 0, ~MSR_CE 225d49747bdSScott Wood rlwinm r4, r4, 0, ~MSR_ME 226d49747bdSScott Wood mtmsr r4 227d49747bdSScott Wood isync 228d49747bdSScott Wood 229d49747bdSScott Wood#define TMP_VIRT_IMMR 0xf0000000 230d49747bdSScott Wood#define DEFAULT_IMMR_VALUE 0xff400000 231d49747bdSScott Wood#define IMMRBAR_BASE 0x0000 232d49747bdSScott Wood 233d49747bdSScott Wood lis r4, immrbase@ha 234d49747bdSScott Wood lwz r4, immrbase@l(r4) 235d49747bdSScott Wood 236d49747bdSScott Wood /* Use DBAT0 to address the current IMMR space */ 237d49747bdSScott Wood 238d49747bdSScott Wood ori r4, r4, 0x002a 239d49747bdSScott Wood mtspr SPRN_DBAT0L, r4 240d49747bdSScott Wood lis r8, TMP_VIRT_IMMR@h 241b595076aSUwe Kleine-König ori r4, r8, 0x001e /* 1 MByte accessible from Kernel Space only */ 242d49747bdSScott Wood mtspr SPRN_DBAT0U, r4 243d49747bdSScott Wood isync 244d49747bdSScott Wood 245d49747bdSScott Wood /* Use DBAT1 to address the original IMMR space */ 246d49747bdSScott Wood 247d49747bdSScott Wood lis r4, DEFAULT_IMMR_VALUE@h 248d49747bdSScott Wood ori r4, r4, 0x002a 249d49747bdSScott Wood mtspr SPRN_DBAT1L, r4 250d49747bdSScott Wood lis r9, (TMP_VIRT_IMMR + 0x01000000)@h 251b595076aSUwe Kleine-König ori r4, r9, 0x001e /* 1 MByte accessible from Kernel Space only */ 252d49747bdSScott Wood mtspr SPRN_DBAT1U, r4 253d49747bdSScott Wood isync 254d49747bdSScott Wood 255d49747bdSScott Wood /* Use DBAT2 to address the beginning of RAM. This isn't done 256d49747bdSScott Wood * using the normal virtual mapping, because with page debugging 257d49747bdSScott Wood * enabled it will be read-only. 258d49747bdSScott Wood */ 259d49747bdSScott Wood 260d49747bdSScott Wood li r4, 0x0002 261d49747bdSScott Wood mtspr SPRN_DBAT2L, r4 262d49747bdSScott Wood lis r4, KERNELBASE@h 263b595076aSUwe Kleine-König ori r4, r4, 0x001e /* 1 MByte accessible from Kernel Space only */ 264d49747bdSScott Wood mtspr SPRN_DBAT2U, r4 265d49747bdSScott Wood isync 266d49747bdSScott Wood 267d49747bdSScott Wood /* Flush the cache with our BAT, as there will be TLB misses 268d49747bdSScott Wood * otherwise if page debugging is enabled, and these misses 269d49747bdSScott Wood * will disturb the PLRU algorithm. 270d49747bdSScott Wood */ 271d49747bdSScott Wood 272d49747bdSScott Wood bl __flush_disable_L1 273d49747bdSScott Wood 274d49747bdSScott Wood /* Keep the i-cache enabled, so the hack below for low-boot 275d49747bdSScott Wood * flash will work. 276d49747bdSScott Wood */ 277d49747bdSScott Wood mfspr r3, SPRN_HID0 278d49747bdSScott Wood ori r3, r3, HID0_ICE 279d49747bdSScott Wood mtspr SPRN_HID0, r3 280d49747bdSScott Wood isync 281d49747bdSScott Wood 282d49747bdSScott Wood lis r6, 0xf515 283d49747bdSScott Wood ori r6, r6, 0x3ae5 284d49747bdSScott Wood 285d49747bdSScott Wood lis r7, mpc83xx_deep_resume@h 286d49747bdSScott Wood ori r7, r7, mpc83xx_deep_resume@l 287d49747bdSScott Wood tophys(r7, r7) 288d49747bdSScott Wood 289d49747bdSScott Wood lis r5, KERNELBASE@h 290d49747bdSScott Wood stw r6, 0(r5) 291d49747bdSScott Wood stw r7, 4(r5) 292d49747bdSScott Wood 293d49747bdSScott Wood /* Reset BARs */ 294d49747bdSScott Wood 295d49747bdSScott Wood li r4, 0 296d49747bdSScott Wood stw r4, 0x0024(r8) 297d49747bdSScott Wood stw r4, 0x002c(r8) 298d49747bdSScott Wood stw r4, 0x0034(r8) 299d49747bdSScott Wood stw r4, 0x003c(r8) 300d49747bdSScott Wood stw r4, 0x0064(r8) 301d49747bdSScott Wood stw r4, 0x006c(r8) 302d49747bdSScott Wood 303d49747bdSScott Wood /* Rev 1 of the 8313 has problems with wakeup events that are 304d49747bdSScott Wood * pending during the transition to deep sleep state (such as if 305d49747bdSScott Wood * the PCI host sets the state to D3 and then D0 in rapid 306d49747bdSScott Wood * succession). This check shrinks the race window somewhat. 307d49747bdSScott Wood * 308d49747bdSScott Wood * See erratum PCI23, though the problem is not limited 309d49747bdSScott Wood * to PCI. 310d49747bdSScott Wood */ 311d49747bdSScott Wood 312d49747bdSScott Wood lwz r3, 0x0b04(r8) 313d49747bdSScott Wood andi. r3, r3, 1 314d49747bdSScott Wood bne- mpc83xx_deep_resume 315d49747bdSScott Wood 316d49747bdSScott Wood /* Move IMMR back to the default location, following the 317d49747bdSScott Wood * procedure specified in the MPC8313 manual. 318d49747bdSScott Wood */ 319d49747bdSScott Wood lwz r4, IMMRBAR_BASE(r8) 320d49747bdSScott Wood isync 321d49747bdSScott Wood lis r4, DEFAULT_IMMR_VALUE@h 322d49747bdSScott Wood stw r4, IMMRBAR_BASE(r8) 323d49747bdSScott Wood lis r4, KERNELBASE@h 324d49747bdSScott Wood lwz r4, 0(r4) 325d49747bdSScott Wood isync 326d49747bdSScott Wood lwz r4, IMMRBAR_BASE(r9) 327d49747bdSScott Wood mr r8, r9 328d49747bdSScott Wood isync 329d49747bdSScott Wood 330d49747bdSScott Wood /* Check the Reset Configuration Word to see whether flash needs 331d49747bdSScott Wood * to be mapped at a low address or a high address. 332d49747bdSScott Wood */ 333d49747bdSScott Wood 334d49747bdSScott Wood lwz r4, 0x0904(r8) 335d49747bdSScott Wood andis. r4, r4, 0x0400 336d49747bdSScott Wood li r4, 0 337d49747bdSScott Wood beq boot_low 338d49747bdSScott Wood lis r4, 0xff80 339d49747bdSScott Woodboot_low: 340d49747bdSScott Wood stw r4, 0x0020(r8) 341d49747bdSScott Wood lis r7, 0x8000 342d49747bdSScott Wood ori r7, r7, 0x0016 343d49747bdSScott Wood 344d49747bdSScott Wood mfspr r5, SPRN_HID0 345d49747bdSScott Wood rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP) 346d49747bdSScott Wood oris r5, r5, HID0_SLEEP@h 347d49747bdSScott Wood mtspr SPRN_HID0, r5 348d49747bdSScott Wood isync 349d49747bdSScott Wood 350d49747bdSScott Wood mfmsr r5 351d49747bdSScott Wood oris r5, r5, MSR_POW@h 352d49747bdSScott Wood 353d49747bdSScott Wood /* Enable the flash mapping at the appropriate address. This 354d49747bdSScott Wood * mapping will override the RAM mapping if booting low, so there's 355d49747bdSScott Wood * no need to disable the latter. This must be done inside the same 356d49747bdSScott Wood * cache line as setting MSR_POW, so that no instruction fetches 357d49747bdSScott Wood * from RAM happen after the flash mapping is turned on. 358d49747bdSScott Wood */ 359d49747bdSScott Wood 360d49747bdSScott Wood .align 5 361d49747bdSScott Wood stw r7, 0x0024(r8) 362d49747bdSScott Wood sync 363d49747bdSScott Wood isync 364d49747bdSScott Wood mtmsr r5 365d49747bdSScott Wood isync 366d49747bdSScott Wood1: b 1b 367d49747bdSScott Wood 368d49747bdSScott Woodmpc83xx_deep_resume: 369d49747bdSScott Wood lis r4, 1f@h 370d49747bdSScott Wood ori r4, r4, 1f@l 371d49747bdSScott Wood tophys(r4, r4) 372d49747bdSScott Wood mtsrr0 r4 373d49747bdSScott Wood 374d49747bdSScott Wood mfmsr r4 375d49747bdSScott Wood rlwinm r4, r4, 0, ~(MSR_IR | MSR_DR) 376d49747bdSScott Wood mtsrr1 r4 377d49747bdSScott Wood 378d49747bdSScott Wood rfi 379d49747bdSScott Wood 380d49747bdSScott Wood1: tlbia 381d49747bdSScott Wood bl __inval_enable_L1 382d49747bdSScott Wood 383d49747bdSScott Wood lis r3, mpc83xx_sleep_save_area@h 384d49747bdSScott Wood ori r3, r3, mpc83xx_sleep_save_area@l 385d49747bdSScott Wood tophys(r3, r3) 386d49747bdSScott Wood 387d49747bdSScott Wood lwz r5, SS_MEMSAVE+0(r3) 388d49747bdSScott Wood lwz r6, SS_MEMSAVE+4(r3) 389d49747bdSScott Wood 390d49747bdSScott Wood stw r5, 0(0) 391d49747bdSScott Wood stw r6, 4(0) 392d49747bdSScott Wood 393d49747bdSScott Wood lwz r5, SS_HID+0(r3) 394d49747bdSScott Wood lwz r6, SS_HID+4(r3) 395d49747bdSScott Wood lwz r7, SS_HID+8(r3) 396d49747bdSScott Wood 397d49747bdSScott Wood mtspr SPRN_HID0, r5 398d49747bdSScott Wood mtspr SPRN_HID1, r6 399d49747bdSScott Wood mtspr SPRN_HID2, r7 400d49747bdSScott Wood 401d49747bdSScott Wood lwz r4, SS_IABR+0(r3) 402d49747bdSScott Wood lwz r5, SS_IABR+4(r3) 403d49747bdSScott Wood lwz r6, SS_IBCR(r3) 404d49747bdSScott Wood lwz r7, SS_DABR+0(r3) 405d49747bdSScott Wood lwz r8, SS_DABR+4(r3) 406d49747bdSScott Wood lwz r9, SS_DBCR(r3) 407d49747bdSScott Wood 408d49747bdSScott Wood mtspr SPRN_IABR, r4 409d49747bdSScott Wood mtspr SPRN_IABR2, r5 410d49747bdSScott Wood mtspr SPRN_IBCR, r6 411d49747bdSScott Wood mtspr SPRN_DABR, r7 412d49747bdSScott Wood mtspr SPRN_DABR2, r8 413d49747bdSScott Wood mtspr SPRN_DBCR, r9 414d49747bdSScott Wood 415d49747bdSScott Wood li r4, 0 416d49747bdSScott Wood addi r6, r3, SS_SR-4 417d49747bdSScott Wood1: lwzu r5, 4(r6) 418d49747bdSScott Wood mtsrin r5, r4 419d49747bdSScott Wood addis r4, r4, 0x1000 420d49747bdSScott Wood cmpwi r4, 0 421d49747bdSScott Wood bne 1b 422d49747bdSScott Wood 423d49747bdSScott Wood lwz r4, SS_DBAT+0x00(r3) 424d49747bdSScott Wood lwz r5, SS_DBAT+0x04(r3) 425d49747bdSScott Wood lwz r6, SS_DBAT+0x08(r3) 426d49747bdSScott Wood lwz r7, SS_DBAT+0x0c(r3) 427d49747bdSScott Wood 428d49747bdSScott Wood mtspr SPRN_DBAT0U, r4 429d49747bdSScott Wood mtspr SPRN_DBAT0L, r5 430d49747bdSScott Wood mtspr SPRN_DBAT1U, r6 431d49747bdSScott Wood mtspr SPRN_DBAT1L, r7 432d49747bdSScott Wood 433d49747bdSScott Wood lwz r4, SS_DBAT+0x10(r3) 434d49747bdSScott Wood lwz r5, SS_DBAT+0x14(r3) 435d49747bdSScott Wood lwz r6, SS_DBAT+0x18(r3) 436d49747bdSScott Wood lwz r7, SS_DBAT+0x1c(r3) 437d49747bdSScott Wood 438d49747bdSScott Wood mtspr SPRN_DBAT2U, r4 439d49747bdSScott Wood mtspr SPRN_DBAT2L, r5 440d49747bdSScott Wood mtspr SPRN_DBAT3U, r6 441d49747bdSScott Wood mtspr SPRN_DBAT3L, r7 442d49747bdSScott Wood 443d49747bdSScott Wood lwz r4, SS_DBAT+0x20(r3) 444d49747bdSScott Wood lwz r5, SS_DBAT+0x24(r3) 445d49747bdSScott Wood lwz r6, SS_DBAT+0x28(r3) 446d49747bdSScott Wood lwz r7, SS_DBAT+0x2c(r3) 447d49747bdSScott Wood 448d49747bdSScott Wood mtspr SPRN_DBAT4U, r4 449d49747bdSScott Wood mtspr SPRN_DBAT4L, r5 450d49747bdSScott Wood mtspr SPRN_DBAT5U, r6 451d49747bdSScott Wood mtspr SPRN_DBAT5L, r7 452d49747bdSScott Wood 453d49747bdSScott Wood lwz r4, SS_DBAT+0x30(r3) 454d49747bdSScott Wood lwz r5, SS_DBAT+0x34(r3) 455d49747bdSScott Wood lwz r6, SS_DBAT+0x38(r3) 456d49747bdSScott Wood lwz r7, SS_DBAT+0x3c(r3) 457d49747bdSScott Wood 458d49747bdSScott Wood mtspr SPRN_DBAT6U, r4 459d49747bdSScott Wood mtspr SPRN_DBAT6L, r5 460d49747bdSScott Wood mtspr SPRN_DBAT7U, r6 461d49747bdSScott Wood mtspr SPRN_DBAT7L, r7 462d49747bdSScott Wood 463d49747bdSScott Wood lwz r4, SS_IBAT+0x00(r3) 464d49747bdSScott Wood lwz r5, SS_IBAT+0x04(r3) 465d49747bdSScott Wood lwz r6, SS_IBAT+0x08(r3) 466d49747bdSScott Wood lwz r7, SS_IBAT+0x0c(r3) 467d49747bdSScott Wood 468d49747bdSScott Wood mtspr SPRN_IBAT0U, r4 469d49747bdSScott Wood mtspr SPRN_IBAT0L, r5 470d49747bdSScott Wood mtspr SPRN_IBAT1U, r6 471d49747bdSScott Wood mtspr SPRN_IBAT1L, r7 472d49747bdSScott Wood 473d49747bdSScott Wood lwz r4, SS_IBAT+0x10(r3) 474d49747bdSScott Wood lwz r5, SS_IBAT+0x14(r3) 475d49747bdSScott Wood lwz r6, SS_IBAT+0x18(r3) 476d49747bdSScott Wood lwz r7, SS_IBAT+0x1c(r3) 477d49747bdSScott Wood 478d49747bdSScott Wood mtspr SPRN_IBAT2U, r4 479d49747bdSScott Wood mtspr SPRN_IBAT2L, r5 480d49747bdSScott Wood mtspr SPRN_IBAT3U, r6 481d49747bdSScott Wood mtspr SPRN_IBAT3L, r7 482d49747bdSScott Wood 483d49747bdSScott Wood lwz r4, SS_IBAT+0x20(r3) 484d49747bdSScott Wood lwz r5, SS_IBAT+0x24(r3) 485d49747bdSScott Wood lwz r6, SS_IBAT+0x28(r3) 486d49747bdSScott Wood lwz r7, SS_IBAT+0x2c(r3) 487d49747bdSScott Wood 488d49747bdSScott Wood mtspr SPRN_IBAT4U, r4 489d49747bdSScott Wood mtspr SPRN_IBAT4L, r5 490d49747bdSScott Wood mtspr SPRN_IBAT5U, r6 491d49747bdSScott Wood mtspr SPRN_IBAT5L, r7 492d49747bdSScott Wood 493d49747bdSScott Wood lwz r4, SS_IBAT+0x30(r3) 494d49747bdSScott Wood lwz r5, SS_IBAT+0x34(r3) 495d49747bdSScott Wood lwz r6, SS_IBAT+0x38(r3) 496d49747bdSScott Wood lwz r7, SS_IBAT+0x3c(r3) 497d49747bdSScott Wood 498d49747bdSScott Wood mtspr SPRN_IBAT6U, r4 499d49747bdSScott Wood mtspr SPRN_IBAT6L, r5 500d49747bdSScott Wood mtspr SPRN_IBAT7U, r6 501d49747bdSScott Wood mtspr SPRN_IBAT7L, r7 502d49747bdSScott Wood 50336da5ff0SChristophe Leroy lwz r4, SS_SPRG+16(r3) 50436da5ff0SChristophe Leroy lwz r5, SS_SPRG+20(r3) 50536da5ff0SChristophe Leroy lwz r6, SS_SPRG+24(r3) 50636da5ff0SChristophe Leroy lwz r7, SS_SPRG+28(r3) 50736da5ff0SChristophe Leroy 50836da5ff0SChristophe Leroy mtspr SPRN_SPRG4, r4 50936da5ff0SChristophe Leroy mtspr SPRN_SPRG5, r5 51036da5ff0SChristophe Leroy mtspr SPRN_SPRG6, r6 51136da5ff0SChristophe Leroy mtspr SPRN_SPRG7, r7 51236da5ff0SChristophe Leroy 513d49747bdSScott Wood lwz r4, SS_SPRG+0(r3) 514d49747bdSScott Wood lwz r5, SS_SPRG+4(r3) 515d49747bdSScott Wood lwz r6, SS_SPRG+8(r3) 516d49747bdSScott Wood lwz r7, SS_SPRG+12(r3) 517d49747bdSScott Wood lwz r8, SS_SDR1(r3) 518d49747bdSScott Wood 519d49747bdSScott Wood mtspr SPRN_SPRG0, r4 520d49747bdSScott Wood mtspr SPRN_SPRG1, r5 521d49747bdSScott Wood mtspr SPRN_SPRG2, r6 522d49747bdSScott Wood mtspr SPRN_SPRG3, r7 523d49747bdSScott Wood mtsdr1 r8 524d49747bdSScott Wood 525d49747bdSScott Wood lwz r4, SS_MSR(r3) 526d49747bdSScott Wood lwz r5, SS_LR(r3) 527d49747bdSScott Wood lwz r6, SS_CR(r3) 528d49747bdSScott Wood lwz r1, SS_SP(r3) 529d49747bdSScott Wood lwz r2, SS_R2(r3) 530d49747bdSScott Wood 531d49747bdSScott Wood mtsrr1 r4 532d49747bdSScott Wood mtsrr0 r5 533d49747bdSScott Wood mtcr r6 534d49747bdSScott Wood 535d49747bdSScott Wood li r4, 0 536d49747bdSScott Wood mtspr SPRN_TBWL, r4 537d49747bdSScott Wood 538d49747bdSScott Wood lwz r4, SS_TB+0(r3) 539d49747bdSScott Wood lwz r5, SS_TB+4(r3) 540d49747bdSScott Wood 541d49747bdSScott Wood mtspr SPRN_TBWU, r4 542d49747bdSScott Wood mtspr SPRN_TBWL, r5 543d49747bdSScott Wood 544d49747bdSScott Wood lmw r12, SS_GPREG(r3) 545d49747bdSScott Wood 546d49747bdSScott Wood /* Kick decrementer */ 547d49747bdSScott Wood li r0, 1 548d49747bdSScott Wood mtdec r0 549d49747bdSScott Wood 550d49747bdSScott Wood rfi 551*7aa85127SChristophe Leroy_ASM_NOKPROBE_SYMBOL(mpc83xx_deep_resume) 552