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Searched refs:medeleg (Results 1 – 4 of 4) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dmachine.c425 VMSTATE_UINTTL(env.medeleg, RISCVCPU),
H A Dcpu.h297 target_ulong medeleg; member
H A Dcpu_helper.c1804 uint64_t deleg = async ? env->mideleg : env->medeleg; in riscv_cpu_do_interrupt()
H A Dcsr.c1770 *val = env->medeleg; in read_medeleg()
1777 env->medeleg = (env->medeleg & ~DELEGABLE_EXCPS) | (val & DELEGABLE_EXCPS); in write_medeleg()