| /openbmc/u-boot/arch/arm/mach-at91/armv7/ |
| H A D | clock.c | 57 unsigned freq, mckr; in at91_clock_init() local
84 mckr = readl(&pmc->mckr); in at91_clock_init()
87 if (mckr & (1 << 12)) in at91_clock_init()
90 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()
94 freq >>= mckr & AT91_PMC_MCKR_PRES_MASK; in at91_clock_init()
96 switch (mckr & AT91_PMC_MCKR_MDIV_MASK) { in at91_clock_init()
124 void at91_mck_init(u32 mckr) in at91_mck_init() argument
129 tmp = readl(&pmc->mckr); in at91_mck_init()
138 tmp |= mckr & (AT91_PMC_MCKR_CSS_MASK | in at91_mck_init()
143 tmp |= mckr & AT91_PMC_MCKR_H32MXDIV; in at91_mck_init()
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| /openbmc/u-boot/arch/arm/mach-at91/arm926ejs/ |
| H A D | clock.c | 115 unsigned freq, mckr; in at91_clock_init() local
155 mckr = readl(&pmc->mckr); in at91_clock_init()
159 gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12)); in at91_clock_init()
161 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()
166 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4)); in at91_clock_init()
168 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()
173 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ? in at91_clock_init()
174 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq; in at91_clock_init()
175 if (mckr & AT91_PMC_MCKR_MDIV_MASK) in at91_clock_init()
185 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) == in at91_clock_init()
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| /openbmc/linux/drivers/clk/at91/ |
| H A D | clk-master.c | 35 u32 mckr; member
93 unsigned int mckr; in clk_master_div_recalc_rate() local
96 regmap_read(master->regmap, master->layout->offset, &mckr); in clk_master_div_recalc_rate()
99 mckr &= layout->mask; in clk_master_div_recalc_rate()
101 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_recalc_rate()
118 unsigned int mckr, div; in clk_master_div_save_context() local
121 regmap_read(master->regmap, master->layout->offset, &mckr); in clk_master_div_save_context()
124 mckr &= master->layout->mask; in clk_master_div_save_context()
125 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK; in clk_master_div_save_context()
138 unsigned int mckr; in clk_master_div_restore_context() local
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| H A D | clk-h32mx.c | 32 unsigned int mckr; in clk_sama5d4_h32mx_recalc_rate() local
34 regmap_read(h32mxclk->regmap, AT91_PMC_MCKR, &mckr); in clk_sama5d4_h32mx_recalc_rate()
35 if (mckr & AT91_PMC_H32MXDIV) in clk_sama5d4_h32mx_recalc_rate()
64 u32 mckr = 0; in clk_sama5d4_h32mx_set_rate() local
70 mckr = AT91_PMC_H32MXDIV; in clk_sama5d4_h32mx_set_rate()
73 AT91_PMC_H32MXDIV, mckr); in clk_sama5d4_h32mx_set_rate()
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| H A D | clk-plldiv.c | 26 unsigned int mckr; in clk_plldiv_recalc_rate() local
28 regmap_read(plldiv->regmap, AT91_PMC_MCKR, &mckr); in clk_plldiv_recalc_rate()
30 if (mckr & AT91_PMC_PLLADIV2) in clk_plldiv_recalc_rate()
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| /openbmc/u-boot/arch/arm/mach-at91/arm920t/ |
| H A D | clock.c | 107 unsigned freq, mckr; in at91_clock_init() local
147 mckr = readl(&pmc->mckr); in at91_clock_init()
148 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK); in at91_clock_init()
151 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */ in at91_clock_init()
154 (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8)); in at91_clock_init()
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| /openbmc/u-boot/arch/arm/mach-at91/ |
| H A D | spl_at91.c | 44 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) { in lowlevel_clock_init()
47 tmp = readl(&pmc->mckr); in lowlevel_clock_init()
50 writel(tmp, &pmc->mckr); in lowlevel_clock_init()
56 writel(tmp, &pmc->mckr); in lowlevel_clock_init()
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| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91_common.h | 26 void at91_mck_init(u32 mckr);
27 void at91_mck_init_down(u32 mckr);
32 void at91_mck_init(u32 mckr);
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| H A D | clk.h | 65 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV; in get_h32mxdiv()
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| H A D | at91_pmc.h | 41 u32 mckr; /* 0x30 Master Clock Register */ member
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| /openbmc/u-boot/drivers/clk/at91/ |
| H A D | clk-plladiv.c | 32 if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2) in at91_plladiv_clk_get_rate()
55 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2), in at91_plladiv_clk_set_rate()
56 &pmc->mckr); in at91_plladiv_clk_set_rate()
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| H A D | clk-h32mx.c | 25 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV) in sama5d4_h32mx_clk_get_rate()
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| /openbmc/linux/drivers/power/reset/ |
| H A D | at91-sama5d2_shdwc.c | 78 u8 mckr; member
168 "r" (at91_shdwc->rcfg->pmc.mckr) in at91_poweroff()
269 .mckr = 0x30,
286 .mckr = 0x28,
303 .mckr = 0x28,
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| /openbmc/u-boot/board/esd/meesc/ |
| H A D | meesc.c | 235 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) | in misc_init_r()
236 AT91SAM9_PMC_MDIV_4, &pmc->mckr); in misc_init_r()
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| /openbmc/linux/arch/arm/mach-at91/ |
| H A D | pm.c | 1320 unsigned long mckr; member
1327 .mckr = 0x30,
1333 .mckr = 0x30,
1338 .mckr = 0x30,
1342 .mckr = 0x30,
1347 .mckr = 0x28,
1351 .mckr = 0x28,
1438 soc_pm.data.pmc_mckr_offset = pmc->mckr; in at91_pm_init()
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