| /openbmc/linux/drivers/gpu/drm/amd/amdkfd/ |
| H A D | kfd_mqd_manager.c | 126 if (gfx_info->max_sh_per_se > KFD_MAX_NUM_SH_PER_SE) { in mqd_symmetrically_map_cu_mask()
129 gfx_info->max_sh_per_se * gfx_info->max_shader_engines); in mqd_symmetrically_map_cu_mask()
148 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) in mqd_symmetrically_map_cu_mask()
194 for (sh = 0; sh < gfx_info->max_sh_per_se; sh++) { in mqd_symmetrically_map_cu_mask()
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| H A D | kfd_topology.c | 1650 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in fill_in_l2_l3_pcache()
1717 for (j = 0; j < gfx_info->max_sh_per_se; j++) { in kfd_fill_cache_non_crat_info()
1973 gfx_info->max_sh_per_se; in kfd_topology_add_device()
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| H A D | kfd_crat.c | 2095 cu->array_count = gfx_info->max_sh_per_se * in kfd_create_vcrat_image_gpu()
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | amdgpu_atomfirmware.c | 793 adev->gfx.config.max_sh_per_se = gfx_info->v24.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
811 adev->gfx.config.max_sh_per_se = gfx_info->v27.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
832 adev->gfx.config.max_sh_per_se = gfx_info->v30.max_sh_per_se; in amdgpu_atomfirmware_get_gfx_info()
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| H A D | gfx_v6_0.c | 1322 adev->gfx.config.max_sh_per_se); in gfx_v6_0_get_rb_active_bitmap()
1363 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v6_0_write_harvested_raster_configs()
1456 adev->gfx.config.max_sh_per_se; in gfx_v6_0_setup_rb()
1461 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1465 ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v6_0_setup_rb()
1489 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_rb()
1537 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v6_0_setup_spi()
1575 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1592 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
1609 adev->gfx.config.max_sh_per_se = 2; in gfx_v6_0_constants_init()
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| H A D | gfx_v7_0.c | 1597 adev->gfx.config.max_sh_per_se); in gfx_v7_0_get_rb_active_bitmap()
1639 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v7_0_write_harvested_raster_configs()
1757 adev->gfx.config.max_sh_per_se; in gfx_v7_0_setup_rb()
1762 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
1765 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v7_0_setup_rb()
1791 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_setup_rb()
3301 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v7_0_wait_for_rlc_serdes()
4220 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4237 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
4255 adev->gfx.config.max_sh_per_se = 1; in gfx_v7_0_gpu_early_init()
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| H A D | gfx_v8_0.c | 1665 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1682 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1729 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1745 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1762 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
1780 adev->gfx.config.max_sh_per_se = 1; in gfx_v8_0_gpu_early_init()
3437 adev->gfx.config.max_sh_per_se); in gfx_v8_0_get_rb_active_bitmap()
3488 unsigned sh_per_se = max_t(unsigned, adev->gfx.config.max_sh_per_se, 1); in gfx_v8_0_write_harvested_raster_configs()
3599 adev->gfx.config.max_sh_per_se; in gfx_v8_0_setup_rb()
3604 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v8_0_setup_rb()
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| H A D | amdgpu_gfx.h | 191 unsigned max_sh_per_se; member
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| H A D | gfx_v9_4_3.c | 1124 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_4_3_xcc_wait_for_rlc_serdes()
3953 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { in gfx_v9_4_3_inst_query_sq_timeout_status()
4022 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; sh_idx++) { in gfx_v9_4_3_inst_reset_sq_timeout_status()
4305 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_4_3_get_cu_info()
4310 adev->gfx.config.max_sh_per_se); in gfx_v9_4_3_get_cu_info()
4316 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_4_3_get_cu_info()
4323 disable_masks[i * adev->gfx.config.max_sh_per_se + j], in gfx_v9_4_3_get_cu_info()
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| H A D | gfx_v9_0.c | 1499 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_init_always_on_cu_mask()
2257 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_rb_active_bitmap()
2268 adev->gfx.config.max_sh_per_se; in gfx_v9_0_setup_rb()
2272 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_setup_rb()
2275 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v9_0_setup_rb()
2438 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_wait_for_rlc_serdes()
4357 adev->gfx.config.max_sh_per_se; in gfx_v9_0_do_edc_gpr_workarounds()
7218 adev->gfx.config.max_sh_per_se > 16) in gfx_v9_0_get_cu_info()
7223 adev->gfx.config.max_sh_per_se); in gfx_v9_0_get_cu_info()
7227 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v9_0_get_cu_info()
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| H A D | amdgpu_debugfs.c | 130 if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_process_reg_op()
256 if ((rd->id.grbm.sh != 0xFFFFFFFF && rd->id.grbm.sh >= adev->gfx.config.max_sh_per_se) || in amdgpu_debugfs_regs2_op()
891 config[no_regs++] = adev->gfx.config.max_sh_per_se; in amdgpu_debugfs_gca_config_read()
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| H A D | gfx_v10_0.c | 4729 adev->gfx.config.max_sh_per_se); in gfx_v10_0_get_rb_active_bitmap()
4741 adev->gfx.config.max_sh_per_se; in gfx_v10_0_setup_rb()
4745 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_setup_rb()
4746 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_setup_rb()
4754 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) * in gfx_v10_0_setup_rb()
4781 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se * in gfx_v10_0_init_pa_sc_tile_steering_override()
4915 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_tcp_harvest()
9336 adev->gfx.config.max_sh_per_se * in gfx_v10_0_set_gds_init()
9425 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v10_0_get_cu_info()
9426 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v10_0_get_cu_info()
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| H A D | gfxhub_v2_1.c | 548 adev->gfx.config.max_sh_per_se * in gfxhub_v2_1_utcl2_harvest()
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| H A D | amdgpu_atombios.c | 728 adev->gfx.config.max_sh_per_se = gfx_info->info.max_sh_per_se; in amdgpu_atombios_get_gfx_info()
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| H A D | gfx_v11_0.c | 1570 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * in gfx_v11_0_get_sa_active_bitmap()
1611 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
1613 adev->gfx.config.max_sh_per_se; in gfx_v11_0_setup_rb()
6265 adev->gfx.config.max_sh_per_se * in gfx_v11_0_set_gds_init()
6349 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { in gfx_v11_0_get_cu_info()
6350 bitmap = i * adev->gfx.config.max_sh_per_se + j; in gfx_v11_0_get_cu_info()
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| H A D | gfx_v9_4_2.c | 1866 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_query_sq_timeout_status()
1899 for (sh_idx = 0; sh_idx < adev->gfx.config.max_sh_per_se; in gfx_v9_4_2_reset_sq_timeout_status()
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| H A D | amdgpu_amdkfd_gfx_v9.c | 1053 sh_cnt = adev->gfx.config.max_sh_per_se; in kgd_gfx_v9_get_cu_occupancy()
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| H A D | amdgpu_discovery.c | 1439 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v1.gc_num_sa_per_se); in amdgpu_discovery_get_gfx_info()
1473 adev->gfx.config.max_sh_per_se = le32_to_cpu(gc_info->v2.gc_num_sh_per_se); in amdgpu_discovery_get_gfx_info()
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| H A D | amdgpu_kms.c | 806 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se; in amdgpu_info_ioctl()
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| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | radeon_kms.c | 465 *value = rdev->config.cik.max_sh_per_se; in radeon_info_ioctl()
467 *value = rdev->config.si.max_sh_per_se; in radeon_info_ioctl()
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| H A D | si.c | 3102 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3119 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3137 rdev->config.si.max_sh_per_se = 2; in si_gpu_init()
3154 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3171 rdev->config.si.max_sh_per_se = 1; in si_gpu_init()
3288 rdev->config.si.max_sh_per_se, in si_gpu_init()
3292 rdev->config.si.max_sh_per_se, in si_gpu_init()
3297 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_gpu_init()
5328 for (j = 0; j < rdev->config.si.max_sh_per_se; j++) { in si_init_ao_cu_mask()
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| H A D | cik.c | 3181 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3198 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3216 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3234 rdev->config.cik.max_sh_per_se = 1; in cik_gpu_init()
3336 rdev->config.cik.max_sh_per_se, in cik_gpu_init()
3341 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_gpu_init()
5787 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_wait_for_rlc_serdes()
6554 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) { in cik_init_ao_cu_mask()
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| H A D | radeon.h | 2127 unsigned max_sh_per_se; member
2158 unsigned max_sh_per_se; member
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| /openbmc/linux/drivers/gpu/drm/amd/include/ |
| H A D | atomfirmware.h | 1759 uint8_t max_sh_per_se; member
1779 uint8_t max_sh_per_se; member
1804 uint8_t max_sh_per_se; member
1839 uint8_t max_sh_per_se; member
1880 uint8_t max_sh_per_se; member
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| /openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | vangogh_ppt.c | 2268 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
2294 aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines; in vangogh_post_smu_init()
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