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Searched refs:m_shift (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/arch/x86/include/asm/uv/
H A Duv_hub.h165 unsigned char m_shift; member
442 paddr = ((paddr << uv_hub_info->m_shift) in uv_soc_phys_ram_to_gpa()
443 >> uv_hub_info->m_shift) | in uv_soc_phys_ram_to_gpa()
475 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | in uv_gpa_to_soc_phys_ram()
504 unsigned int m_shift = uv_hub_info->m_shift; in uv_gpa_to_offset() local
506 if (m_shift) in uv_gpa_to_offset()
507 return (gpa << m_shift) >> m_shift; in uv_gpa_to_offset()
/openbmc/u-boot/arch/arm/mach-tegra/tegra20/
H A Dclock.c368 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
370 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
372 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
374 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
376 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
378 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
380 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
382 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
384 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c437 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
439 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
441 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
443 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
445 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
447 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
449 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
451 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
453 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/openbmc/u-boot/arch/arm/mach-tegra/tegra30/
H A Dclock.c417 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x0F,
419 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 0, .p_mask = 0,
421 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
423 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
425 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
427 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
429 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
431 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
433 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
/openbmc/linux/drivers/clk/ingenic/
H A Dx1830-cgu.c118 .m_shift = 20,
141 .m_shift = 20,
164 .m_shift = 20,
187 .m_shift = 20,
H A Dx1000-cgu.c223 .m_shift = 24,
246 .m_shift = 24,
367 .m_shift = 13,
H A Djz4760-cgu.c98 .m_shift = 23,
123 .m_shift = 23,
H A Dcgu.h56 u8 m_shift, m_bits, m_offset; member
H A Djz4770-cgu.c108 .m_shift = 24,
132 .m_shift = 24,
H A Djz4725b-cgu.c60 .m_shift = 23,
H A Djz4740-cgu.c75 .m_shift = 23,
H A Djz4755-cgu.c57 .m_shift = 23,
H A Dcgu.c95 m = (ctl >> pll_info->m_shift) & GENMASK(pll_info->m_bits - 1, 0); in ingenic_pll_recalc_rate()
222 ctl &= ~(GENMASK(pll_info->m_bits - 1, 0) << pll_info->m_shift); in ingenic_pll_set_rate()
223 ctl |= (m - pll_info->m_offset) << pll_info->m_shift; in ingenic_pll_set_rate()
H A Djz4780-cgu.c276 .m_shift = 19, \
/openbmc/linux/drivers/staging/media/atomisp/pci/isp/kernels/csc/csc_1.0/
H A Dia_css_csc.host.c41 to->m_shift = (int16_t)from->fraction_bits; in ia_css_encode_cc()
77 csc->m_shift); in ia_css_cc_dump()
H A Dia_css_csc_param.h22 u16 m_shift; member
/openbmc/u-boot/arch/arm/mach-tegra/tegra124/
H A Dclock.c577 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
579 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
581 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
583 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
585 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x01,
587 { .m_shift = 0, .m_mask = 0x1F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
589 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x0F,
591 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
593 { .m_shift = 0, .m_mask = 0x0F, .n_shift = 8, .n_mask = 0x3FF, .p_shift = 20, .p_mask = 0x07,
595 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0xF,
/openbmc/u-boot/arch/arm/mach-tegra/tegra210/
H A Dclock.c646 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
648 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
650 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 10, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
652 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
654 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 16, .p_mask = 0x1F,
656 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 11, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x07,
658 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 20, .p_mask = 0x1F,
660 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 0, .p_mask = 0,
662 { .m_shift = 0, .m_mask = 0, .n_shift = 0, .n_mask = 0, .p_shift = 0, .p_mask = 0,
664 { .m_shift = 0, .m_mask = 0xFF, .n_shift = 8, .n_mask = 0xFF, .p_shift = 19, .p_mask = 0x1F,
/openbmc/u-boot/arch/arm/mach-tegra/
H A Dclock.c102 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()
147 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
552 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()
599 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift); in clock_set_rate()
600 base_reg |= m << pllinfo->m_shift; in clock_set_rate()
H A Dcpu.c187 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h390 u32 m_shift:5; /* DIVM_SHIFT */ member
/openbmc/linux/arch/x86/kernel/apic/
H A Dx2apic_uv_x.c1215 unsigned char m_shift; member
1237 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; in get_mn()
1251 hi->m_shift = mn.m_shift; in uv_init_hub_info()
1290 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); in uv_init_hub_info()