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Searched refs:ldr (Results 1 – 25 of 342) sorted by relevance

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/openbmc/u-boot/arch/arm/mach-aspeed/ast2500/
H A Dplatform.S254 ldr r0, =0x1e782024 @ Set Timer3 Reload
257 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
258 ldr r1, =0x00040000
261 ldr r0, =0x1e782030 @ Enable Timer3
266 ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout
270 ldr r1, [r0]
277 ldr r0, =0x1e78203C @ Disable Timer3
282 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
283 ldr r1, =0x00040000
288 ldr r0, =0x1e620084
[all …]
/openbmc/u-boot/board/freescale/mx7ulp_evk/
H A Dplugin.S9 ldr r2, =0x403f0000
10 ldr r3, =0x00000000
13 ldr r2, =0x403e0000
14 ldr r3, =0x01000020
16 ldr r3, =0x01000000
18 ldr r3, =0x80808080
20 ldr r3, =0x00140000
22 ldr r3, =0x00000004
24 ldr r3, =0x00000002
26 ldr r3, =0x00000001
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/
H A Dlowlevel_init.S38 ldr r0, =EINT_ENABLE0
40 ldr r0, =EINT_ENABLE1
48 ldr r8, PSC_GEM_FLAG_CLEAR
49 ldr r6, MDCTL_GEM
50 ldr r7, [r6]
55 ldr r6, PTCMD
56 ldr r7, [r6]
62 ldr r6, PTSTAT
63 ldr r7, [r6]
69 ldr r6, MDSTAT_GEM
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S104 ldr r0, =0x1e782024 @ Set Timer3 Reload
107 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
108 ldr r1, =0x00040000
111 ldr r0, =0x1e782030 @ Enable Timer3
112 ldr r1, [r0]
117 ldr r0, =0x1e6c0090 @ Check ISR for Timer3 timeout
121 ldr r1, [r0]
128 ldr r0, =0x1e782030 @ Disable Timer3
129 ldr r1, [r0]
133 ldr r0, =0x1e6c0038 @ Clear Timer3 ISR
[all …]
/openbmc/u-boot/board/freescale/mx6ullevk/
H A Dplugin.S10 ldr r0, =IOMUXC_BASE_ADDR
11 ldr r1, =0x000C0000
13 ldr r1, =0x00000000
15 ldr r1, =0x00000030
17 ldr r1, =0x00000030
21 ldr r1, =0x000C0030
24 ldr r1, =0x00000000
27 ldr r1, =0x00000030
32 ldr r1, =0x00020000
35 ldr r1, =0x00000030
[all …]
/openbmc/u-boot/board/freescale/mx6sllevk/
H A Dplugin.S10 ldr r0, =IOMUXC_BASE_ADDR
11 ldr r1, =0x00080000
13 ldr r1, =0x00000000
15 ldr r1, =0x00000030
19 ldr r1, =0x00020000
21 ldr r1, =0x00003030
27 ldr r1, =0x00020000
29 ldr r1, =0x00000030
39 ldr r1, =0x00082030
42 ldr r0, =MMDC_P0_BASE_ADDR
[all …]
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S30 ldr r7, =S5PC100_GPIO_BASE
31 ldr r8, =S5PC100_GPIO_BASE
33 ldr r2, =S5PC110_PRO_ID
34 ldr r0, [r2]
39 ldr r8, =S5PC110_GPIO_BASE
45 ldr r0, =S5PC110_RST_STAT
46 ldr r1, [r0]
55 ldr r1, [r0, #0x0] @ GPIO_CON_OFFSET
60 ldr r1, [r0, #0x4] @ GPIO_DAT_OFFSET
86 ldr r0, =0xe0f00000
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2600/
H A Dplatform.S78 ldr r1, =SCU_PROT_KEY1
80 ldr r1, =SCU_PROT_KEY2
89 ldr r0, =SCU_REV_ID
90 ldr r0, [r0]
92 ldr r1, =REV_ID_AST2600A0
97 ldr r1, =SCU_HW_STRAP1
98 ldr r1, [r1]
145 ldr r1, =SCU_SMP_READY
168 ldr r0, =SCU_SMP_READY
169 ldr r0, [r0]
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dlowlevel.S31 ldr x0, =GICD_BASE
33 ldr x1, =GICC_BASE
36 ldr x2, =DCFG_CCSR_SVR
37 ldr w2, [x2]
40 ldr w4, =SVR_DEV(SVR_LS1043A)
46 ldr x2, =SCFG_GIC400_ALIGN
47 ldr w2, [x2]
50 ldr x0, =GICD_BASE_64K
52 ldr x1, =GICC_BASE_64K
90 ldr x0, =CCI_AUX_CONTROL_BASE(20)
[all …]
/openbmc/linux/arch/arm/mach-imx/
H A Dsuspend-imx6.S78 ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
84 ldr r6, [r11, #L2X0_CACHE_SYNC]
99 ldr r6, [r0, #PM_INFO_MMDC_IO_NUM_OFFSET]
100 ldr r7, =PM_INFO_MMDC_IO_VAL_OFFSET
103 ldr r8, [r7], #0x4
104 ldr r9, [r7], #0x4
117 ldr r7, =MX6Q_MMDC_MPDGCTRL0
118 ldr r6, [r11, r7]
122 ldr r6, [r11, r7]
127 ldr r6, [r11, r7]
[all …]
H A Dsuspend-imx53.S45 ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET]
50 ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET]
53 ldr r5, [r2], #12 /* IOMUXC register offset */
54 ldr r6, [r3, r5] /* current value */
61 ldr r1, [r0, #SUSPEND_INFO_MX53_M4IF_V_OFFSET]
62 ldr r2,[r1, #M4IF_MCR0_OFFSET]
68 ldr r2,[r1, #M4IF_MCR0_OFFSET]
73 ldr r1, [r0, #SUSPEND_INFO_MX53_IO_COUNT_OFFSET]
78 ldr r3, [r0, #SUSPEND_INFO_MX53_IOMUXC_V_OFFSET]
81 ldr r5, [r2], #4 /* IOMUXC register offset */
[all …]
/openbmc/linux/drivers/memory/
H A Dti-emif-sram-pm.S46 ldr r0, [r4, #EMIF_PM_BASE_ADDR_VIRT_OFFSET]
47 ldr r2, [r4, #EMIF_PM_REGS_VIRT_OFFSET]
50 ldr r1, [r0, #EMIF_SDRAM_CONFIG]
53 ldr r1, [r0, #EMIF_SDRAM_REFRESH_CONTROL]
56 ldr r1, [r0, #EMIF_SDRAM_TIMING_1]
59 ldr r1, [r0, #EMIF_SDRAM_TIMING_2]
62 ldr r1, [r0, #EMIF_SDRAM_TIMING_3]
65 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CONTROL]
68 ldr r1, [r0, #EMIF_POWER_MANAGEMENT_CTRL_SHDW]
71 ldr r1, [r0, #EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG]
[all …]
/openbmc/u-boot/arch/arm/mach-imx/mx5/
H A Dlowlevel_init.S32 ldr r0, =0xC0 | /* tag RAM */ \
39 ldr r3, [r4, #ROM_SI_REV]
62 ldr r0, =AIPS1_BASE_ADDR
63 ldr r1, =0x77777777
66 ldr r0, =AIPS2_BASE_ADDR
82 ldr r0, =M4IF_BASE_ADDR
84 ldr r1, =0x00000203
89 ldr r1, =0x00120125
92 ldr r1, =0x001901A3
99 ldr r0, =\pll
[all …]
/openbmc/u-boot/board/armadeus/apf27/
H A Dlowlevel_init.S22 ldr r0, =GPCR
23 ldr r1, =ACFG_GPCR_VAL
24 ldr r5, [r0]
31 ldr r0, =CSCR
33 ldr r1, [r0]
64 ldr r0, =IMX_ESD_BASE
65 ldr r4, =ESDMISC_SDRAM_RDY
66 2: ldr r1, [r0, #ESDMISC_ROF]
71 ldr r0, =IMX_ESD_BASE
72 ldr r4, =ACFG_ESDMISC_VAL
[all …]
/openbmc/u-boot/arch/arm/cpu/arm920t/ep93xx/
H A Dlowlevel_init.S29 ldr r3, =SDRAM_BASE
46 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
58 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_INIT | \
65 ldr r4, =0x10
77 ldr r4, =0x01e0
81 ldr r4, =(EP93XX_SDRAMCTRL_GLOBALCFG_CKE | \
86 ldr r4, [r2]
89 ldr r4, =EP93XX_SDRAMCTRL_GLOBALCFG_CKE
104 ldr r1, =0xf00dface
105 ldr r2, =0xdeadbeef
[all …]
/openbmc/linux/arch/arm/mach-at91/
H A Dpm_suspend.S42 2: ldr r8, [pmc, #AT91_PMC_SR]
54 1: ldr r7, [pmc, #AT91_PMC_SR]
65 1: ldr r7, [pmc, #AT91_PMC_SR]
99 ldr r7, .sfrbu
101 ldr r9, [r7, #AT91_SFRBU_25LDOCR]
107 ldr r10, =AT91_SFRBU_25LDOCR_LDOANAKEY
130 ldr r2, .sramc_base
131 ldr r3, .sramc_phy_base
132 ldr r7, .pm_mode
137 ldr tmp1, [r2, #UDDRC_PCTRL_0]
[all …]
/openbmc/openbmc/meta-facebook/meta-yosemitev2/recipes-bsp/u-boot/u-boot-aspeed-sdk/
H A D0001-board-aspeed-Add-Mux-for-yosemitev2.patch16 ldr r2, =0x00000800
20 + ldr r0, =0x1e780024
21 + ldr r1, [r0]
25 + ldr r0, =0x1e780020
26 + ldr r1, [r0]
35 + ldr r0, =0x1e6e2080
36 + ldr r1, [r0]
37 + ldr r2, =0xBFBFFFFF
41 + ldr r0, =0x1e6e2084
42 + ldr r1, [r0]
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dsleep43xx.S69 ldr r2, [r3, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
74 ldr r1, get_l2cache_base
87 ldr r1, kernel_flush
104 ldr r1, kernel_flush
120 ldr r3, [r4, #AMX3_PM_RO_SRAM_DATA_VIRT_OFFSET]
123 ldr r0, [r2, #L2X0_AUX_CTRL]
125 ldr r0, [r2, #L310_PREFETCH_CTRL]
128 ldr r0, l2_val
131 ldr r0, [r2, #L2X0_CLEAN_INV_WAY]
132 ldr r1, l2_val
[all …]
H A Dsleep34xx.S76 ldr r2, [r3] @ value for offset
145 ldr r4, omap3_do_wfi_sram_addr
146 ldr r5, [r4]
162 ldr r1, kernel_flush
181 ldr r1, kernel_flush
206 ldr r4, sdrc_power @ read the SDRC_POWER register
207 ldr r5, [r4] @ read the contents of SDRC_POWER
252 ldr r4, cm_idlest_ckgen
254 ldr r5, [r4]
258 ldr r4, cm_idlest1_core
[all …]
/openbmc/u-boot/arch/arm/cpu/arm926ejs/spear/
H A Dspr_lowlevel_init.S25 ldr sp,SRAM_STACK_V
32 ldr r0,DDR_07_V
33 ldr r1,[r0]
34 ldr r2,DDR_ACTIVE_V
37 ldr r0,DDR_57_V
38 ldr r1,[r0]
39 ldr r2,CYCLES_MASK_V
41 ldr r2,REFRESH_CYCLES_V
44 ldr r0,DDR_07_V
45 ldr r1,[r0]
[all …]
/openbmc/linux/tools/testing/selftests/arm64/abi/
H A Dsyscall-abi-asm.S86 ldr x2, [x2, :lo12:svcr_in]
92 ldr x2, =za_in
110 ldr x2, =gpr_in
122 ldr x28, [x2], #8
128 ldr x2, =svcr_in
131 ldr x2, =fpr_in
154 ldr x2, =z_in
155 ldr z0, [x2, #0, MUL VL]
156 ldr z1, [x2, #1, MUL VL]
157 ldr z2, [x2, #2, MUL VL]
[all …]
/openbmc/u-boot/board/samsung/smdkc100/
H A Dlowlevel_init.S25 ldr r8, =S5PC100_GPIO_BASE
28 ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
33 ldr r0, =S5PC100_SROMC_BASE
34 ldr r1, =0x9
38 ldr r0, =S5PC100_VIC0_BASE @0xE4000000
39 ldr r1, =S5PC100_VIC1_BASE @0xE4000000
40 ldr r2, =S5PC100_VIC2_BASE @0xE4000000
73 ldr r8, =S5PC100_CLOCK_BASE @ 0xE0100000
76 ldr r1, =0x00011110
78 ldr r1, =0x1
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/arm32/
H A Ddebug_ll.S23 ldr r0, =SG_REVISION
24 ldr r1, [r0]
33 ldr r0, =SG_IECTRL
34 ldr r1, [r0]
40 ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
52 ldr r0, =SG_LOADPINCTRL
56 ldr r0, =SC_CLKCTRL
57 ldr r1, [r0]
61 ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
71 ldr r0, =SG_IECTRL
[all …]
/openbmc/u-boot/arch/arm/mach-orion5x/
H A Dlowlevel_init.S75 ldr r2, =ORION5X_REGS_PHY_BASE
79 ldr r3, =0xD0000000
87 ldr r0, =0x00000001
94 ldr r0, =0x00000030
108 ldr r0, =SDRAM_CONFIG
112 ldr r0, =SDRAM_CONTROL
116 ldr r0, =SDRAM_ADDR_CTRL
120 ldr r0, =SDRAM_BANK0_SIZE
125 ldr r0, =SDRAM_OPEN_PAGE_EN
129 ldr r0, =SDRAM_TIME_CTRL_LOW
[all …]
/openbmc/u-boot/board/freescale/mx35pdk/
H A Dlowlevel_init.S21 ldr \tmp, =IIM_BASE_ADDR
22 ldr \ret, [\tmp, #IIM_SREV]
32 ldr r0, =DBG_BASE_ADDR
33 ldr r1, =DBG_CSCR_U_CONFIG
35 ldr r1, =DBG_CSCR_L_CONFIG
37 ldr r1, =DBG_CSCR_A_CONFIG
43 ldr r0, =CCM_BASE_ADDR
46 ldr r1, [r0, #CLKCTL_COSR]
54 ldr r2, =CCM_CCMR_CONFIG
61 ldr r2, [r0, #CLKCTL_PDR0]
[all …]

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