1*83d290c5STom Rini/* SPDX-License-Identifier: GPL-2.0+ */ 2bcc05c7aStrem/* 3bcc05c7aStrem * (C) Copyright 2013 Philippe Reynes <tremyfr@yahoo.fr> 4bcc05c7aStrem */ 5bcc05c7aStrem 6bcc05c7aStrem#include <config.h> 7bcc05c7aStrem#include <generated/asm-offsets.h> 8bcc05c7aStrem#include <asm/macro.h> 9bcc05c7aStrem#include <asm/arch/imx-regs.h> 10bcc05c7aStrem#include "apf27.h" 11bcc05c7aStrem 12bcc05c7aStrem .macro init_aipi 13bcc05c7aStrem /* 14bcc05c7aStrem * setup AIPI1 and AIPI2 15bcc05c7aStrem */ 16bcc05c7aStrem write32 AIPI1_PSR0, ACFG_AIPI1_PSR0_VAL 17bcc05c7aStrem write32 AIPI1_PSR1, ACFG_AIPI1_PSR1_VAL 18bcc05c7aStrem write32 AIPI2_PSR0, ACFG_AIPI2_PSR0_VAL 19bcc05c7aStrem write32 AIPI2_PSR1, ACFG_AIPI2_PSR1_VAL 20bcc05c7aStrem 21bcc05c7aStrem /* Change SDRAM signal strengh */ 22bcc05c7aStrem ldr r0, =GPCR 23bcc05c7aStrem ldr r1, =ACFG_GPCR_VAL 24bcc05c7aStrem ldr r5, [r0] 25bcc05c7aStrem orr r5, r5, r1 26bcc05c7aStrem str r5, [r0] 27bcc05c7aStrem 28bcc05c7aStrem .endm /* init_aipi */ 29bcc05c7aStrem 30bcc05c7aStrem .macro init_clock 31bcc05c7aStrem ldr r0, =CSCR 32bcc05c7aStrem /* disable MPLL/SPLL first */ 33bcc05c7aStrem ldr r1, [r0] 34bcc05c7aStrem bic r1, r1, #(CSCR_MPEN|CSCR_SPEN) 35bcc05c7aStrem str r1, [r0] 36bcc05c7aStrem 37bcc05c7aStrem /* 38bcc05c7aStrem * pll clock initialization predefined in apf27.h 39bcc05c7aStrem */ 40bcc05c7aStrem write32 MPCTL0, ACFG_MPCTL0_VAL 41bcc05c7aStrem write32 SPCTL0, ACFG_SPCTL0_VAL 42bcc05c7aStrem 43bcc05c7aStrem write32 CSCR, ACFG_CSCR_VAL|CSCR_MPLL_RESTART|CSCR_SPLL_RESTART 44bcc05c7aStrem 45bcc05c7aStrem /* 46bcc05c7aStrem * add some delay here 47bcc05c7aStrem */ 48bcc05c7aStrem mov r1, #0x1000 49bcc05c7aStrem 1: subs r1, r1, #0x1 50bcc05c7aStrem bne 1b 51bcc05c7aStrem 52bcc05c7aStrem /* peripheral clock divider */ 53bcc05c7aStrem write32 PCDR0, ACFG_PCDR0_VAL 54bcc05c7aStrem write32 PCDR1, ACFG_PCDR1_VAL 55bcc05c7aStrem 56bcc05c7aStrem /* Configure PCCR0 and PCCR1 */ 57bcc05c7aStrem write32 PCCR0, ACFG_PCCR0_VAL 58bcc05c7aStrem write32 PCCR1, ACFG_PCCR1_VAL 59bcc05c7aStrem 60bcc05c7aStrem .endm /* init_clock */ 61bcc05c7aStrem 62bcc05c7aStrem .macro init_ddr 63bcc05c7aStrem /* wait for SDRAM/LPDDR ready (SDRAMRDY) */ 64bcc05c7aStrem ldr r0, =IMX_ESD_BASE 65bcc05c7aStrem ldr r4, =ESDMISC_SDRAM_RDY 66bcc05c7aStrem2: ldr r1, [r0, #ESDMISC_ROF] 67bcc05c7aStrem ands r1, r1, r4 68bcc05c7aStrem bpl 2b 69bcc05c7aStrem 70bcc05c7aStrem /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */ 71bcc05c7aStrem ldr r0, =IMX_ESD_BASE 72bcc05c7aStrem ldr r4, =ACFG_ESDMISC_VAL 73bcc05c7aStrem orr r1, r4, #ESDMISC_MDDR_DL_RST 74bcc05c7aStrem str r1, [r0, #ESDMISC_ROF] 75bcc05c7aStrem 76bcc05c7aStrem /* Hold for more than 200ns */ 77bcc05c7aStrem ldr r1, =0x10000 78bcc05c7aStrem1: subs r1, r1, #0x1 79bcc05c7aStrem bne 1b 80bcc05c7aStrem 81bcc05c7aStrem str r4, [r0] 82bcc05c7aStrem 83bcc05c7aStrem ldr r0, =IMX_ESD_BASE 84bcc05c7aStrem ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL 85bcc05c7aStrem str r1, [r0, #ESDCFG0_ROF] 86bcc05c7aStrem 87bcc05c7aStrem ldr r0, =IMX_ESD_BASE 88bcc05c7aStrem ldr r1, =ACFG_PRECHARGE_CMD 89bcc05c7aStrem str r1, [r0, #ESDCTL0_ROF] 90bcc05c7aStrem 91bcc05c7aStrem /* write8(0xA0001000, any value) */ 92bcc05c7aStrem ldr r1, =PHYS_SDRAM_1+ACFG_SDRAM_PRECHARGE_ALL_VAL 93bcc05c7aStrem strb r2, [r1] 94bcc05c7aStrem 95bcc05c7aStrem ldr r1, =ACFG_AUTOREFRESH_CMD 96bcc05c7aStrem str r1, [r0, #ESDCTL0_ROF] 97bcc05c7aStrem 98bcc05c7aStrem ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */ 99bcc05c7aStrem 100bcc05c7aStrem ldr r6,=0x7 /* load loop counter */ 101bcc05c7aStrem1: str r5,[r4] /* run auto-refresh cycle to array 0 */ 102bcc05c7aStrem subs r6,r6,#1 103bcc05c7aStrem bne 1b 104bcc05c7aStrem 105bcc05c7aStrem ldr r1, =ACFG_SET_MODE_REG_CMD 106bcc05c7aStrem str r1, [r0, #ESDCTL0_ROF] 107bcc05c7aStrem 108bcc05c7aStrem /* set standard mode register */ 109bcc05c7aStrem ldr r4, = PHYS_SDRAM_1+ACFG_SDRAM_MODE_REGISTER_VAL 110bcc05c7aStrem strb r2, [r4] 111bcc05c7aStrem 112bcc05c7aStrem /* set extended mode register */ 113bcc05c7aStrem ldr r4, =PHYS_SDRAM_1+ACFG_SDRAM_EXT_MODE_REGISTER_VAL 114bcc05c7aStrem strb r5, [r4] 115bcc05c7aStrem 116bcc05c7aStrem ldr r1, =ACFG_NORMAL_RW_CMD 117bcc05c7aStrem str r1, [r0, #ESDCTL0_ROF] 118bcc05c7aStrem 119bcc05c7aStrem /* 2nd sdram */ 120bcc05c7aStrem ldr r0, =IMX_ESD_BASE 121bcc05c7aStrem ldr r1, =ACFG_SDRAM_ESDCFG_REGISTER_VAL 122bcc05c7aStrem str r1, [r0, #ESDCFG1_ROF] 123bcc05c7aStrem 124bcc05c7aStrem ldr r0, =IMX_ESD_BASE 125bcc05c7aStrem ldr r1, =ACFG_PRECHARGE_CMD 126bcc05c7aStrem str r1, [r0, #ESDCTL1_ROF] 127bcc05c7aStrem 128bcc05c7aStrem /* write8(0xB0001000, any value) */ 129bcc05c7aStrem ldr r1, =PHYS_SDRAM_2+ACFG_SDRAM_PRECHARGE_ALL_VAL 130bcc05c7aStrem strb r2, [r1] 131bcc05c7aStrem 132bcc05c7aStrem ldr r1, =ACFG_AUTOREFRESH_CMD 133bcc05c7aStrem str r1, [r0, #ESDCTL1_ROF] 134bcc05c7aStrem 135bcc05c7aStrem ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */ 136bcc05c7aStrem 137bcc05c7aStrem ldr r6,=0x7 /* load loop counter */ 138bcc05c7aStrem1: str r5,[r4] /* run auto-refresh cycle to array 0 */ 139bcc05c7aStrem subs r6,r6,#1 140bcc05c7aStrem bne 1b 141bcc05c7aStrem 142bcc05c7aStrem ldr r1, =ACFG_SET_MODE_REG_CMD 143bcc05c7aStrem str r1, [r0, #ESDCTL1_ROF] 144bcc05c7aStrem 145bcc05c7aStrem /* set standard mode register */ 146bcc05c7aStrem ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_MODE_REGISTER_VAL 147bcc05c7aStrem strb r2, [r4] 148bcc05c7aStrem 149bcc05c7aStrem /* set extended mode register */ 150bcc05c7aStrem ldr r4, =PHYS_SDRAM_2+ACFG_SDRAM_EXT_MODE_REGISTER_VAL 151bcc05c7aStrem strb r2, [r4] 152bcc05c7aStrem 153bcc05c7aStrem ldr r1, =ACFG_NORMAL_RW_CMD 154bcc05c7aStrem str r1, [r0, #ESDCTL1_ROF] 155bcc05c7aStrem .endm /* init_ddr */ 156bcc05c7aStrem 157bcc05c7aStrem.globl lowlevel_init 158bcc05c7aStremlowlevel_init: 159bcc05c7aStrem 160bcc05c7aStrem init_aipi 161bcc05c7aStrem init_clock 162bcc05c7aStrem#ifdef CONFIG_SPL_BUILD 163bcc05c7aStrem init_ddr 164bcc05c7aStrem#endif 165bcc05c7aStrem 166bcc05c7aStrem mov pc, lr 167