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Searched refs:ip_versions (Results 1 – 25 of 90) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_discovery.c326 if ((adev->ip_versions[UVD_HWIP][1] == IP_VERSION(3, 0, 1)) && in amdgpu_discovery_harvest_config_quirk()
327 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 2))) { in amdgpu_discovery_harvest_config_quirk()
1352 adev->ip_versions[hw_ip][ip->instance_number] = in amdgpu_discovery_reg_base_init()
1378 if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 2, 0) && in amdgpu_discovery_harvest_ip()
1379 adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 3)) { in amdgpu_discovery_harvest_ip()
1622 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_common_ip_blocks()
1659 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_common_ip_blocks()
1668 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_discovery_set_gmc_ip_blocks()
1705 adev->ip_versions[GC_HWIP][0]); in amdgpu_discovery_set_gmc_ip_blocks()
1713 switch (adev->ip_versions[OSSSYS_HWIP][0]) { in amdgpu_discovery_set_ih_ip_blocks()
[all …]
H A Dhdp_v4_0.c54 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0) || in hdp_v4_0_invalidate_hdp()
55 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 2)) in hdp_v4_0_invalidate_hdp()
87 if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0)) in hdp_v4_0_reset_ras_error_count()
99 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) || in hdp_v4_0_update_clock_gating()
100 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) || in hdp_v4_0_update_clock_gating()
101 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) || in hdp_v4_0_update_clock_gating()
102 adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) { in hdp_v4_0_update_clock_gating()
144 switch (adev->ip_versions[HDP_HWIP][0]) { in hdp_v4_0_init_registers()
154 if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0)) in hdp_v4_0_init_registers()
H A Dgmc_v9_0.c642 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) in gmc_v9_0_process_interrupt()
656 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_process_interrupt()
673 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v9_0_process_interrupt()
773 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in gmc_v9_0_use_invalidate_semaphore()
774 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3)) in gmc_v9_0_use_invalidate_semaphore()
825 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)) { in gmc_v9_0_flush_gpu_tlb()
835 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && in gmc_v9_0_flush_gpu_tlb()
897 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(9, 4, 2))) in gmc_v9_0_flush_gpu_tlb()
970 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 0)); in gmc_v9_0_flush_gpu_tlb_pasid()
985 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 3) && in gmc_v9_0_flush_gpu_tlb_pasid()
[all …]
H A Dathub_v3_0.c39 switch (adev->ip_versions[ATHUB_HWIP][0]) { in athub_v3_0_get_cg_cntl()
52 switch (adev->ip_versions[ATHUB_HWIP][0]) { in athub_v3_0_set_cg_cntl()
102 switch (adev->ip_versions[ATHUB_HWIP][0]) { in athub_v3_0_set_clockgating()
H A Dgmc_v10_0.c148 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_process_interrupt()
281 (adev->ip_versions[GC_HWIP][0] < IP_VERSION(10, 3, 0))) in gmc_v10_0_flush_vm_hub()
683 switch (adev->ip_versions[UMC_HWIP][0]) { in gmc_v10_0_set_umc_funcs()
700 switch (adev->ip_versions[MMHUB_HWIP][0]) { in gmc_v10_0_set_mmhub_funcs()
714 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_set_gfxhub_funcs()
828 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_mc_init()
895 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
913 switch (adev->ip_versions[GC_HWIP][0]) { in gmc_v10_0_sw_init()
1202 if (adev->in_s0ix && adev->ip_versions[DF_HWIP][0] > IP_VERSION(3, 0, 2)) { in gmc_v10_0_set_clockgating_state()
1211 if (adev->ip_versions[ATHUB_HWIP][0] >= IP_VERSION(2, 1, 0)) in gmc_v10_0_set_clockgating_state()
[all …]
H A Dnbio_v7_2.c62 switch (adev->ip_versions[NBIO_HWIP][0]) { in nbio_v7_2_get_rev_id()
81 switch (adev->ip_versions[NBIO_HWIP][0]) { in nbio_v7_2_mc_access_enable()
265 switch (adev->ip_versions[NBIO_HWIP][0]) { in nbio_v7_2_update_medium_grain_light_sleep()
372 switch (adev->ip_versions[NBIO_HWIP][0]) { in nbio_v7_2_init_registers()
397 switch (adev->ip_versions[NBIO_HWIP][0]) { in nbio_v7_2_init_registers()
H A Dsoc15.c177 if (adev->ip_versions[VCE_HWIP][0]) { in soc15_query_video_codecs()
178 switch (adev->ip_versions[VCE_HWIP][0]) { in soc15_query_video_codecs()
190 switch (adev->ip_versions[UVD_HWIP][0]) { in soc15_query_video_codecs()
327 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 0) || in soc15_get_xclk()
328 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(12, 0, 1) || in soc15_get_xclk()
329 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 6)) in soc15_get_xclk()
331 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 0) || in soc15_get_xclk()
332 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(10, 0, 1)) in soc15_get_xclk()
526 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_asic_reset_method()
625 switch (adev->ip_versions[MP1_HWIP][0]) { in soc15_supports_baco()
[all …]
H A Dvega20_ih.c321 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 2, 1)) && in vega20_ih_irq_init()
334 if ((adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0)) || in vega20_ih_irq_init()
335 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) { in vega20_ih_irq_init()
364 if (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 0) || in vega20_ih_irq_init()
365 adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2)) in vega20_ih_irq_init()
573 (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2))) in vega20_ih_sw_init()
590 if (adev->ip_versions[OSSSYS_HWIP][0] != IP_VERSION(4, 4, 2)) { in vega20_ih_sw_init()
H A Damdgpu_reset.c41 switch (adev->ip_versions[MP1_HWIP][0]) { in amdgpu_reset_init()
63 switch (adev->ip_versions[MP1_HWIP][0]) { in amdgpu_reset_fini()
H A Dmmhub_v2_0.c154 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_print_l2_protection_fault_status()
571 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_clock_gating()
604 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_clock_gating()
628 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_update_medium_grain_light_sleep()
654 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_set_clockgating()
679 switch (adev->ip_versions[MMHUB_HWIP][0]) { in mmhub_v2_0_get_clockgating()
H A Dsdma_v4_0.c472 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_golden_registers()
542 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_setup_ulv()
581 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) || in sdma_v4_0_init_microcode()
582 adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 4, 0)) { in sdma_v4_0_init_microcode()
981 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && in sdma_v4_0_ctx_switch_enable()
1258 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_init_pg()
1701 switch (adev->ip_versions[SDMA0_HWIP][0]) { in sdma_v4_0_fw_support_paging_queue()
1726 if ((adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 0, 0)) && in sdma_v4_0_early_init()
1826 if (adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(4, 2, 2) && i >= 5) in sdma_v4_0_sw_init()
1846 if (adev->ip_versions[SDMA0_HWIP][0] >= IP_VERSION(4, 0, 0) && in sdma_v4_0_sw_init()
[all …]
H A Dsoc21.c156 switch (adev->ip_versions[UVD_HWIP][0]) { in soc21_query_video_codecs()
376 switch (adev->ip_versions[MP1_HWIP][0]) { in soc21_asic_reset_method()
450 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_need_full_reset()
576 switch (adev->ip_versions[GC_HWIP][0]) { in soc21_common_early_init()
857 switch (adev->ip_versions[NBIO_HWIP][0]) { in soc21_common_set_clockgating_state()
879 switch (adev->ip_versions[LSDMA_HWIP][0]) { in soc21_common_set_powergating_state()
H A Damdgpu_ras.c204 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && in amdgpu_ras_debugfs_read()
205 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { in amdgpu_ras_debugfs_read()
614 if (obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && in amdgpu_ras_sysfs_read()
615 obj->adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { in amdgpu_ras_sysfs_read()
1214 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && in amdgpu_ras_query_error_count_helper()
1215 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4)) { in amdgpu_ras_query_error_count_helper()
1917 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2))) in amdgpu_ras_log_on_err_counter()
1922 if (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 2) && in amdgpu_ras_log_on_err_counter()
1923 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(11, 0, 4) && in amdgpu_ras_log_on_err_counter()
1924 adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 0)) { in amdgpu_ras_log_on_err_counter()
[all …]
H A Daldebaran.c38 if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && in aldebaran_is_mode2_default()
160 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2) && in aldebaran_mode2_perform_reset()
342 if (reset_context->reset_req_dev->ip_versions[MP1_HWIP][0] == in aldebaran_mode2_restore_hwcontext()
H A Dpsp_v13_0.c85 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_v13_0_init_microcode()
167 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) ? in psp_v13_0_wait_for_bootloader()
191 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) { in psp_v13_0_wait_for_bootloader_steady_state()
738 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 10)) { in psp_v13_0_fatal_error_recovery_quirk()
H A Dathub_v2_0.c80 switch (adev->ip_versions[ATHUB_HWIP][0]) { in athub_v2_0_set_clockgating()
H A Dathub_v2_1.c73 switch (adev->ip_versions[ATHUB_HWIP][0]) { in athub_v2_1_set_clockgating()
H A Damdgpu_ucode.c1064 switch (adev->ip_versions[MP0_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1115 switch (adev->ip_versions[MP1_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1141 switch (adev->ip_versions[SDMA0_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1185 switch (adev->ip_versions[UVD_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1210 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) in amdgpu_ucode_legacy_naming()
1223 switch (adev->ip_versions[GC_HWIP][0]) { in amdgpu_ucode_legacy_naming()
1276 uint32_t version = adev->ip_versions[block_type][0]; in amdgpu_ucode_ip_version_decode()
H A Dathub_v1_0.c71 switch (adev->ip_versions[ATHUB_HWIP][0]) { in athub_v1_0_set_clockgating()
H A Dgfx_v9_0.c898 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_init_golden_registers()
954 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && in gfx_v9_0_init_golden_registers()
955 (adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 2))) in gfx_v9_0_init_golden_registers()
1098 if ((adev->ip_versions[GC_HWIP][0] != IP_VERSION(9, 4, 1)) && in gfx_v9_0_check_fw_write_wait()
1105 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_fw_write_wait()
1209 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) && in check_if_enlarge_doorbell_range()
1222 switch (adev->ip_versions[GC_HWIP][0]) { in gfx_v9_0_check_if_need_gfxoff()
1333 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 2) || in gfx_v9_0_load_mec2_fw_bin_support()
1334 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 4, 1) || in gfx_v9_0_load_mec2_fw_bin_support()
1335 adev->ip_versions[GC_HWIP][0] == IP_VERSION(9, 3, 0)) in gfx_v9_0_load_mec2_fw_bin_support()
[all …]
H A Damdgpu_psp.c103 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_check_pmfw_centralized_cstate_management()
131 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_init_sriov_microcode()
165 switch (adev->ip_versions[MP0_HWIP][0]) { in psp_early_init()
337 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6)) in psp_get_runtime_db_entry()
416 adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2); in psp_sw_init()
776 switch (psp->adev->ip_versions[MP0_HWIP][0]) { in psp_boottime_tmr()
831 switch (psp->adev->ip_versions[MP0_HWIP][0]) { in psp_skip_tmr()
1218 if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) || in psp_xgmi_terminate()
1219 (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && in psp_xgmi_terminate()
1316 return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) && in psp_xgmi_peer_link_info_supported()
[all …]
H A Dnbio_v4_3.c341 if (adev->ip_versions[NBIO_HWIP][0] == IP_VERSION(4, 3, 0)) { in nbio_v4_3_init_registers()
395 if (!(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 4, 0)) && in nbio_v4_3_program_aspm()
396 !(adev->ip_versions[PCIE_HWIP][0] == IP_VERSION(7, 6, 0))) in nbio_v4_3_program_aspm()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dyellow_carp_ppt.c1027 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1029 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1030 (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1034 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1036 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1037 (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
1041 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 8)) in yellow_carp_get_umd_pstate_clk_default()
1043 if ((adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 1) || in yellow_carp_get_umd_pstate_clk_default()
1044 (adev->ip_versions[MP1_HWIP][0]) == IP_VERSION(13, 0, 3)) in yellow_carp_get_umd_pstate_clk_default()
/openbmc/linux/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c104 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 9)) || in smu_v11_0_init_microcode()
105 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 7)))) in smu_v11_0_init_microcode()
216 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_check_fw_version()
249 adev->ip_versions[MP1_HWIP][0]); in smu_v11_0_check_fw_version()
477 size_t size = adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) ? in smu_v11_0_init_power()
734 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 11) || in smu_v11_0_init_display_count()
735 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 5, 0) || in smu_v11_0_init_display_count()
736 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 12) || in smu_v11_0_init_display_count()
737 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 13)) in smu_v11_0_init_display_count()
1106 switch (adev->ip_versions[MP1_HWIP][0]) { in smu_v11_0_gfx_off_control()
[all …]
H A Dnavi10_ppt.c348 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && in navi10_get_allowed_feature_mask()
357 (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && in navi10_get_allowed_feature_mask()
919 switch (adev->ip_versions[MP1_HWIP][0]) { in navi1x_get_smu_metrics_data()
929 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && smu_version > 0x00351F00) || in navi1x_get_smu_metrics_data()
930 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && smu_version > 0x002A3B00)) in navi1x_get_smu_metrics_data()
1730 switch (adev->ip_versions[MP1_HWIP][0]) { in navi10_populate_umd_state_clk()
2772 if (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0) || in navi10_need_umc_cdr_workaround()
2773 adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) in navi10_need_umc_cdr_workaround()
2881 if (((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 0)) && (pmfw_version >= 0x2a3500)) || in navi10_run_umc_cdr_workaround()
2882 ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(11, 0, 5)) && (pmfw_version >= 0x351D00))) { in navi10_run_umc_cdr_workaround()
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