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Searched refs:intel_de_rmw (Results 1 – 25 of 44) sorted by relevance

12

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c371 intel_de_rmw(dev_priv, reg, 0, FDI_FS_ERRC_ENABLE | FDI_FE_ERRC_ENABLE); in intel_fdi_normal_train()
443 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), in ilk_fdi_link_train()
445 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), in ilk_fdi_link_train()
534 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
585 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
707 intel_de_rmw(dev_priv, FDI_TX_CTL(pipe), in ivb_manual_fdi_link_train()
710 intel_de_rmw(dev_priv, FDI_RX_CTL(pipe), in ivb_manual_fdi_link_train()
819 intel_de_rmw(dev_priv, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
846 intel_de_rmw(dev_priv, DDI_BUF_CTL(PORT_E), DDI_BUF_CTL_ENABLE, 0); in hsw_fdi_link_train()
850 intel_de_rmw(dev_priv, DP_TP_CTL(PORT_E), DP_TP_CTL_ENABLE, 0); in hsw_fdi_link_train()
[all …]
H A Dicl_dsi.c228 intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST); in icl_dsi_frame_update()
251 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
261 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
267 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val); in dsi_program_swing_and_deemphasis()
271 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), in dsi_program_swing_and_deemphasis()
315 intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK, in configure_dual_link_mode()
404 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port), in gen11_dsi_enable_io_power()
431 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0); in gen11_dsi_config_phy_lanes_sequence()
433 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy), in gen11_dsi_config_phy_lanes_sequence()
439 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), in gen11_dsi_config_phy_lanes_sequence()
[all …]
H A Dintel_combo_phy.c84 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
306 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), in intel_combo_phy_power_up_lanes()
364 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW8(phy), in icl_combo_phys_init()
367 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); in icl_combo_phys_init()
368 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), in icl_combo_phys_init()
399 intel_de_rmw(dev_priv, ICL_PHY_MISC(phy), 0, in icl_combo_phys_uninit()
403 intel_de_rmw(dev_priv, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); in icl_combo_phys_uninit()
H A Dintel_audio.c264 intel_de_rmw(i915, G4X_AUD_CNTL_ST, G4X_ELD_ADDRESS_MASK, 0); in g4x_audio_codec_get_config()
281 intel_de_rmw(i915, G4X_AUD_CNTL_ST, in g4x_audio_codec_disable()
299 intel_de_rmw(i915, G4X_AUD_CNTL_ST, in g4x_audio_codec_enable()
313 intel_de_rmw(i915, G4X_AUD_CNTL_ST, in g4x_audio_codec_enable()
325 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), in hsw_dp_audio_config_update()
398 intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), in hsw_audio_codec_disable()
407 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, in hsw_audio_codec_disable()
414 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, in hsw_audio_codec_disable()
543 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, in hsw_audio_codec_enable()
549 intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, in hsw_audio_codec_enable()
[all …]
H A Dvlv_dsi.c341 intel_de_rmw(dev_priv, MIPI_CTRL(port), 0, GLK_MIPIIO_ENABLE); in glk_dsi_enable_io()
344 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_enable_io()
349 intel_de_rmw(dev_priv, MIPI_CTRL(port), in glk_dsi_enable_io()
383 intel_de_rmw(dev_priv, MIPI_CTRL(PORT_A), 0, GLK_MIPIIO_RESET_RELEASED); in glk_dsi_device_ready()
388 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_device_ready()
393 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_device_ready()
402 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_device_ready()
406 intel_de_rmw(dev_priv, MIPI_DEVICE_READY(port), in glk_dsi_device_ready()
410 intel_de_rmw(dev_priv, MIPI_CTRL(port), GLK_LP_WAKE, 0); in glk_dsi_device_ready()
442 intel_de_rmw(dev_priv, BXT_MIPI_PORT_CTRL(port), 0, LP_OUTPUT_HOLD); in bxt_dsi_device_ready()
[all …]
H A Dintel_display_power_well.c356 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); in hsw_power_well_enable()
369 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); in hsw_power_well_enable()
395 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); in hsw_power_well_disable()
422 intel_de_rmw(dev_priv, regs->driver, 0, HSW_PWR_WELL_CTL_REQ(pw_idx)); in icl_combo_phy_aux_power_well_enable()
426 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), in icl_combo_phy_aux_power_well_enable()
434 intel_de_rmw(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), in icl_combo_phy_aux_power_well_enable()
450 intel_de_rmw(dev_priv, ICL_PORT_CL_DW12(phy), in icl_combo_phy_aux_power_well_disable()
453 intel_de_rmw(dev_priv, regs->driver, HSW_PWR_WELL_CTL_REQ(pw_idx), 0); in icl_combo_phy_aux_power_well_disable()
518 intel_de_rmw(dev_priv, DP_AUX_CH_CTL(aux_ch), in icl_tc_phy_aux_power_well_enable()
521 intel_de_rmw(dev_priv, regs->driver, in icl_tc_phy_aux_power_well_enable()
[all …]
H A Dintel_pch_display.c323 intel_de_rmw(dev_priv, reg, TRANS_ENABLE, 0); in ilk_disable_pch_transcoder()
331 intel_de_rmw(dev_priv, TRANS_CHICKEN2(pipe), in ilk_disable_pch_transcoder()
458 intel_de_rmw(dev_priv, TRANS_DP_CTL(pipe), in ilk_pch_post_disable()
463 intel_de_rmw(dev_priv, PCH_DPLL_SEL, in ilk_pch_post_disable()
574 intel_de_rmw(dev_priv, LPT_TRANSCONF, TRANS_ENABLE, 0); in lpt_disable_pch_transcoder()
581 intel_de_rmw(dev_priv, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); in lpt_disable_pch_transcoder()
H A Dintel_dpio_phy.c392 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask); in _bxt_ddi_phy_init()
411 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy), IREF0RC_OFFSET_MASK, in _bxt_ddi_phy_init()
414 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy), IREF1RC_OFFSET_MASK, in _bxt_ddi_phy_init()
418 intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0, in _bxt_ddi_phy_init()
422 intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0, in _bxt_ddi_phy_init()
442 intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy), in _bxt_ddi_phy_init()
449 intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS); in _bxt_ddi_phy_init()
458 intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0); in bxt_ddi_phy_uninit()
460 intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0); in bxt_ddi_phy_uninit()
H A Dintel_ddi.c684 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), in intel_ddi_toggle_hdcp_bits()
1125 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val, in icl_ddi_combo_vswing_program()
1142 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy), in icl_ddi_combo_vswing_program()
1154 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), in icl_ddi_combo_vswing_program()
1165 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy), in icl_ddi_combo_vswing_program()
1199 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), in icl_combo_phy_set_signal_levels()
1205 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), in icl_combo_phy_set_signal_levels()
1238 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), in icl_mg_phy_set_signal_levels()
1240 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), in icl_mg_phy_set_signal_levels()
1250 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), in icl_mg_phy_set_signal_levels()
[all …]
H A Dintel_dpll_mgr.c647 intel_de_rmw(dev_priv, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0); in hsw_ddi_wrpll_disable()
663 intel_de_rmw(dev_priv, SPLL_CTL, SPLL_PLL_ENABLE, 0); in hsw_ddi_spll_disable()
1273 intel_de_rmw(dev_priv, DPLL_CTRL1, in skl_ddi_pll_write_ctrl1()
1293 intel_de_rmw(dev_priv, regs[id].ctl, 0, LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
1312 intel_de_rmw(dev_priv, regs[id].ctl, LCPLL_PLL_ENABLE, 0); in skl_ddi_pll_disable()
1928 intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL); in bxt_ddi_pll_enable()
1931 intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_enable()
1941 intel_de_rmw(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), in bxt_ddi_pll_enable()
1945 intel_de_rmw(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch), in bxt_ddi_pll_enable()
1949 intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 0), in bxt_ddi_pll_enable()
[all …]
H A Dintel_psr.c320 intel_de_rmw(dev_priv, psr_imr_reg(dev_priv, cpu_transcoder), in psr_irq_control()
384 val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0); in intel_psr_irq_handler()
404 intel_de_rmw(dev_priv, psr_imr_reg(dev_priv, cpu_transcoder), in intel_psr_irq_handler()
691 intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), in hsw_activate_psr1()
832 intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder), in psr2_program_idle_frames()
1375 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
1378 intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
1439 intel_de_rmw(dev_priv, TRANS_EXITLINE(cpu_transcoder), EXITLINE_MASK, in intel_psr_enable_source()
1443 intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, in intel_psr_enable_source()
1455 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, in intel_psr_enable_source()
[all …]
H A Dintel_display_power.c1066 intel_de_rmw(dev_priv, reg, DBUF_POWER_REQUEST, in gen9_dbuf_slice_set()
1143 intel_de_rmw(dev_priv, DBUF_CTL_S(slice), in gen12_dbuf_slices_config()
1174 intel_de_rmw(dev_priv, MBUS_ABOX_CTL(i), mask, val); in icl_mbus_init()
1312 intel_de_rmw(dev_priv, LCPLL_CTL, 0, LCPLL_POWER_DOWN_ALLOW); in hsw_disable_lcpll()
1356 intel_de_rmw(dev_priv, LCPLL_CTL, LCPLL_CD_SOURCE_FCLK, 0); in hsw_restore_lcpll()
1398 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, in hsw_enable_pc8()
1433 intel_de_rmw(dev_priv, reg, reset_bits, enable ? reset_bits : 0); in intel_pch_reset_handshake()
1636 intel_de_rmw(dev_priv, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1654 intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, 0, in icl_display_core_init()
1676 intel_de_rmw(dev_priv, DC_STATE_EN, in icl_display_core_init()
[all …]
H A Dintel_dmc.c322 intel_de_rmw(i915, DC_STATE_DEBUG, 0, in gen9_set_dc_state_debugmask()
443 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
447 intel_de_rmw(i915, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
458 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, in mtl_pipedmc_clock_gating_wa()
478 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); in intel_dmc_enable_pipe()
480 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); in intel_dmc_enable_pipe()
491 intel_de_rmw(i915, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); in intel_dmc_disable_pipe()
493 intel_de_rmw(i915, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); in intel_dmc_disable_pipe()
H A Dintel_cx0_phy.c85 intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane), in intel_clear_response_ready_flag()
2415 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL, in intel_program_port_clock_ctl()
2436 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), in intel_program_port_clock_ctl()
2471 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), in intel_cx0_powerdown_change_sequence()
2486 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), in intel_cx0_powerdown_change_sequence()
2500 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), in intel_cx0_setup_powerdown()
2503 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port), in intel_cx0_setup_powerdown()
2557 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, in intel_cx0_phy_lane_reset()
2566 intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port), in intel_cx0_phy_lane_reset()
2585 intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0); in intel_cx0_phy_lane_reset()
[all …]
H A Dintel_pmdemand.c97 intel_de_rmw(i915, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); in intel_pmdemand_init()
456 intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(0), in intel_pmdemand_program_dbuf()
459 intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, in intel_pmdemand_program_dbuf()
561 intel_de_rmw(i915, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, in intel_pmdemand_program_params()
H A Dvlv_dsi_pll.c308 intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0); in bxt_dsi_pll_disable()
558 intel_de_rmw(dev_priv, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE); in bxt_dsi_pll_enable()
586 intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); in bxt_dsi_reset_clocks()
588 intel_de_rmw(dev_priv, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); in bxt_dsi_reset_clocks()
H A Dintel_hotplug_irq.c994 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, in mtp_ddi_hpd_detection_setup()
1003 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, in mtp_ddi_hpd_enable_detection()
1010 intel_de_rmw(i915, SHOTPLUG_CTL_TC, in mtp_tc_hpd_detection_setup()
1019 intel_de_rmw(i915, SHOTPLUG_CTL_DDI, in mtp_tc_hpd_enable_detection()
1035 intel_de_rmw(i915, SOUTH_CHICKEN1, 0, val); in mtp_hpd_invert()
1077 intel_de_rmw(i915, XELPDP_PORT_HOTPLUG_CTL(hpd_pin), in _xelpdp_pica_hpd_detection_setup()
1116 intel_de_rmw(i915, PICAINTERRUPT_IMR, hotplug_irqs, in xelpdp_hpd_irq_setup()
H A Dintel_dsi_vbt.c419 intel_de_rmw(dev_priv, SHOTPLUG_CTL_DDI, in icl_native_gpio_set_value()
429 intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON, in icl_native_gpio_set_value()
436 intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE, in icl_native_gpio_set_value()
443 intel_de_rmw(dev_priv, GPIO(dev_priv, index), in icl_native_gpio_set_value()
452 intel_de_rmw(dev_priv, GPIO(dev_priv, index), in icl_native_gpio_set_value()
H A Dintel_dvo.c192 intel_de_rmw(i915, DVO(port), DVO_ENABLE, 0); in intel_disable_dvo()
209 intel_de_rmw(i915, DVO(port), 0, DVO_ENABLE); in intel_enable_dvo()
455 dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE); in intel_dvo_init_dev()
H A Dintel_dkl_phy.c94 intel_de_rmw(i915, DKL_REG_MMIO(reg), clear, set); in intel_dkl_phy_rmw()
H A Dintel_lvds.c322 intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); in intel_enable_lvds()
324 intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON); in intel_enable_lvds()
342 intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0); in intel_disable_lvds()
347 intel_de_rmw(dev_priv, lvds_encoder->reg, LVDS_PORT_EN, 0); in intel_disable_lvds()
H A Dintel_dpt.c333 intel_de_rmw(i915, PLANE_CHICKEN(pipe, plane_id), in intel_dpt_configure()
338 intel_de_rmw(i915, CHICKEN_MISC_2, in intel_dpt_configure()
H A Dintel_backlight.c355 intel_de_rmw(i915, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); in lpt_disable_backlight()
365 intel_de_rmw(i915, BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE, 0); in pch_disable_backlight()
367 intel_de_rmw(i915, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); in pch_disable_backlight()
381 intel_de_rmw(i915, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0); in i965_disable_backlight()
392 intel_de_rmw(i915, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0); in vlv_disable_backlight()
403 intel_de_rmw(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), in bxt_disable_backlight()
407 intel_de_rmw(i915, UTIL_PIN_CTL, UTIL_PIN_ENABLE, 0); in bxt_disable_backlight()
418 intel_de_rmw(i915, BXT_BLC_PWM_CTL(panel->backlight.controller), in cnp_disable_backlight()
481 intel_de_rmw(i915, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY, in lpt_enable_backlight()
485 intel_de_rmw(i915, SOUTH_CHICKEN1, SPT_PWM_GRANULARITY, in lpt_enable_backlight()
H A Dintel_de.h45 intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set) in intel_de_rmw() function
H A Dintel_modeset_setup.c910 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS); in intel_early_display_was()
917 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES); in intel_early_display_was()
921 intel_de_rmw(i915, CHICKEN_PAR1_1, in intel_early_display_was()
923 intel_de_rmw(i915, CHICKEN_MISC_2, in intel_early_display_was()

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