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Searched refs:intel_de_read (Results 1 – 25 of 62) sorted by relevance

123

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_fdi.c35 cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; in assert_fdi_tx()
37 cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; in assert_fdi_tx()
59 cur_state = intel_de_read(dev_priv, FDI_RX_CTL(pipe)) & FDI_RX_ENABLE; in assert_fdi_rx()
88 cur_state = intel_de_read(i915, FDI_TX_CTL(pipe)) & FDI_TX_PLL_ENABLE; in assert_fdi_tx_pll_enabled()
98 cur_state = intel_de_read(i915, FDI_RX_CTL(pipe)) & FDI_RX_PLL_ENABLE; in assert_fdi_rx_pll()
214 intel_de_read(i915, FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK; in intel_fdi_pll_freq_update()
289 temp = intel_de_read(dev_priv, SOUTH_CHICKEN1); in cpt_set_fdi_bc_bifurcation()
294 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
297 intel_de_read(dev_priv, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation()
344 temp = intel_de_read(dev_priv, reg); in intel_fdi_normal_train()
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H A Dintel_pch_display.c106 val = intel_de_read(dev_priv, PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
116 u32 val = intel_de_read(dev_priv, hdmi_reg); in ibx_sanitize_pch_hdmi_port()
135 u32 val = intel_de_read(dev_priv, dp_reg); in ibx_sanitize_pch_dp_port()
226 intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
228 intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
230 intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
233 intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
235 intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
237 intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
239 intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder))); in ilk_pch_transcoder_set_timings()
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H A Dintel_combo_phy.c59 val = intel_de_read(dev_priv, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
95 u32 val = intel_de_read(dev_priv, reg); in check_phy_reg()
157 return intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
159 return !(intel_de_read(dev_priv, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
161 (intel_de_read(dev_priv, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
335 val = intel_de_read(dev_priv, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
349 val = intel_de_read(dev_priv, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
355 val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
H A Dintel_crt.c88 val = intel_de_read(dev_priv, adpa_reg); in intel_crt_port_enabled()
125 tmp = intel_de_read(dev_priv, crt->adpa_reg); in intel_crt_get_flags()
481 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
505 adpa = intel_de_read(dev_priv, crt->adpa_reg); in ilk_crt_detect_hotplug()
540 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
556 adpa = intel_de_read(dev_priv, crt->adpa_reg); in valleyview_crt_detect_hotplug()
607 stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
710 save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); in intel_crt_load_detect()
711 save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); in intel_crt_load_detect()
712 vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); in intel_crt_load_detect()
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H A Dintel_pps.c98 intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN, in vlv_power_sequencer_kick()
112 DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in vlv_power_sequencer_kick()
122 pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; in vlv_power_sequencer_kick()
275 return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON; in pps_has_pp_on()
280 return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD; in pps_has_vdd_on()
295 u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & in vlv_initial_pps_pipe()
370 return intel_de_read(i915, SOUTH_CHICKEN1) & ICP_SECOND_PPS_IO_SELECT; in intel_pps_is_valid()
537 return (intel_de_read(dev_priv, _pp_stat_reg(intel_dp)) & PP_ON) != 0; in edp_have_panel_power()
550 return intel_de_read(dev_priv, _pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; in edp_have_panel_vdd()
570 intel_de_read(dev_priv, _pp_stat_reg(intel_dp)), in intel_pps_check_power_unlocked()
[all …]
H A Dintel_backlight.c147 return intel_de_read(i915, BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
154 return intel_de_read(i915, BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
163 val = intel_de_read(i915, BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
184 return intel_de_read(i915, VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in vlv_get_backlight()
192 return intel_de_read(i915, BXT_BLC_PWM_DUTY(panel->backlight.controller)); in bxt_get_backlight()
210 val = intel_de_read(i915, BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
220 tmp = intel_de_read(i915, BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
248 tmp = intel_de_read(i915, BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
259 tmp = intel_de_read(i915, VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
348 tmp = intel_de_read(i915, BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
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H A Dintel_display_power_well.c295 ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0; in hsw_power_well_requesters()
296 ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0; in hsw_power_well_requesters()
298 ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0; in hsw_power_well_requesters()
299 ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0; in hsw_power_well_requesters()
321 wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) & in hsw_wait_for_power_well_disable()
593 val = intel_de_read(dev_priv, regs->driver); in hsw_power_well_enabled()
603 val |= intel_de_read(dev_priv, regs->bios); in hsw_power_well_enabled()
611 (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9), in assert_can_enable_dc9()
614 intel_de_read(dev_priv, DC_STATE_EN) & in assert_can_enable_dc9()
618 intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) & in assert_can_enable_dc9()
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H A Dintel_dpll_mgr.c488 val = intel_de_read(dev_priv, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
490 hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id)); in ibx_pch_dpll_get_hw_state()
491 hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id)); in ibx_pch_dpll_get_hw_state()
503 val = intel_de_read(dev_priv, PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
687 val = intel_de_read(dev_priv, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
707 val = intel_de_read(dev_priv, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1167 if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT) in hsw_update_dpll_ref_clks()
1338 val = intel_de_read(dev_priv, regs[id].ctl); in skl_ddi_pll_get_hw_state()
1342 val = intel_de_read(dev_priv, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1347 hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1); in skl_ddi_pll_get_hw_state()
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H A Dintel_fifo_underrun.c102 if ((intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
129 if (old && intel_de_read(dev_priv, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
152 u32 err_int = intel_de_read(dev_priv, GEN7_ERR_INT); in ivb_check_fifo_underruns()
183 intel_de_read(dev_priv, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
239 u32 serr_int = intel_de_read(dev_priv, SERR_INT); in cpt_check_pch_fifo_underruns()
272 if (old && intel_de_read(dev_priv, SERR_INT) & in cpt_set_fifo_underrun_reporting()
421 underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) & in intel_cpu_fifo_underrun_irq_handler()
H A Dicl_dsi.c55 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK) in header_credits_available()
62 return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK) in payload_credits_available()
134 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) & in wait_for_cmds_dispatched_to_panel()
183 tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
247 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy)); in dsi_program_swing_and_deemphasis()
257 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); in dsi_program_swing_and_deemphasis()
295 dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg); in configure_dual_link_mode()
441 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy)); in gen11_dsi_config_phy_lanes_sequence()
452 tmp = intel_de_read(dev_priv, in gen11_dsi_config_phy_lanes_sequence()
472 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy)); in gen11_dsi_voltage_swing_program_seq()
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H A Dvlv_dsi.c123 u32 val = intel_de_read(dev_priv, reg); in read_data()
242 if (cmd == intel_de_read(dev_priv, MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
348 u32 tmp = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in glk_dsi_enable_io()
363 !(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY); in glk_dsi_enable_io()
387 if (!(intel_de_read(dev_priv, MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
448 val = intel_de_read(dev_priv, MIPI_DEVICE_READY(port)); in bxt_dsi_device_ready()
633 temp = intel_de_read(dev_priv, port_ctrl); in intel_dsi_port_enable()
959 bool enabled = intel_de_read(dev_priv, ctrl_reg) & DPI_ENABLE; in intel_dsi_get_hw_state()
968 enabled = intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
972 u32 tmp = intel_de_read(dev_priv, in intel_dsi_get_hw_state()
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H A Dintel_pch_refclk.c17 if (wait_for_us(intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
23 if (wait_for_us((intel_de_read(dev_priv, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
234 if ((intel_de_read(dev_priv, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) in lpt_get_iclkip()
397 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in spll_uses_pch_ssc()
398 u32 ctl = intel_de_read(dev_priv, SPLL_CTL); in spll_uses_pch_ssc()
417 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP); in wrpll_uses_pch_ssc()
418 u32 ctl = intel_de_read(dev_priv, WRPLL_CTL(id)); in wrpll_uses_pch_ssc()
531 u32 temp = intel_de_read(dev_priv, PCH_DPLL(i)); in ilk_init_pch_refclk()
552 val = intel_de_read(dev_priv, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
H A Dintel_tc.c269 lane_mask = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia)); in intel_tc_port_get_lane_mask()
284 pin_mask = intel_de_read(i915, PORT_TX_DFLEXPA1(tc->phy_fia)); in intel_tc_port_get_pin_assignment_mask()
364 val = intel_de_read(i915, PORT_TX_DFLEXDPMLE1(tc->phy_fia)); in intel_tc_port_set_fia_lane_count()
462 fia_isr = intel_de_read(i915, PORT_TX_DFLEXDPSP(tc->phy_fia)); in icl_tc_phy_hpd_live_status()
463 pch_isr = intel_de_read(i915, SDEISR); in icl_tc_phy_hpd_live_status()
499 val = intel_de_read(i915, PORT_TX_DFLEXDPPMS(tc->phy_fia)); in icl_tc_phy_is_ready()
518 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); in icl_tc_phy_take_ownership()
543 val = intel_de_read(i915, PORT_TX_DFLEXDPCSSS(tc->phy_fia)); in icl_tc_phy_is_owned()
700 val = intel_de_read(i915, PORT_TX_DFLEXDPSP(FIA1)); in tgl_tc_phy_init()
747 cpu_isr = intel_de_read(i915, GEN11_DE_HPD_ISR); in adlp_tc_phy_hpd_live_status()
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H A Dintel_vrr.c223 return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; in intel_vrr_is_push_sent()
261 trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); in intel_vrr_get_config()
274 crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; in intel_vrr_get_config()
275 crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; in intel_vrr_get_config()
276 crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; in intel_vrr_get_config()
H A Dintel_ddi.c180 ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & in mtl_wait_ddi_buf_idle()
195 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) & in intel_wait_ddi_buf_idle()
228 ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE), in intel_wait_ddi_buf_active()
231 ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE), in intel_wait_ddi_buf_active()
354 u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; in icl_calc_tbt_pll_link()
640 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_disable_transcoder_func()
718 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); in intel_ddi_connector_get_hw_state()
776 tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port)); in intel_ddi_get_encoder_pipes()
781 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
822 tmp = intel_de_read(dev_priv, in intel_ddi_get_encoder_pipes()
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H A Dintel_display.c317 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); in assert_transcoder()
388 intel_de_read(dev_priv, dpll_reg) & port_mask, in vlv_wait_port_ready()
432 val = intel_de_read(dev_priv, reg); in intel_enable_transcoder()
471 val = intel_de_read(dev_priv, reg); in intel_disable_transcoder()
703 tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe)); in icl_set_pipe_chicken()
1460 u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe)); in glk_pipe_scaler_clock_gating_wa()
1732 intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); in i9xx_pfit_enable()
2027 intel_de_read(dev_priv, PFIT_CONTROL)); in i9xx_pfit_disable()
2416 bool bios_lvds_use_ssc = intel_de_read(dev_priv, in intel_panel_sanitize_ssc()
2598 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; in intel_pipe_is_interlaced()
[all …]
H A Dintel_lvds.c94 val = intel_de_read(i915, lvds_reg); in intel_lvds_port_enabled()
133 tmp = intel_de_read(dev_priv, lvds_encoder->reg); in intel_lvds_get_config()
151 tmp = intel_de_read(dev_priv, PFIT_CONTROL); in intel_lvds_get_config()
164 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
166 val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
171 val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
175 val = intel_de_read(dev_priv, PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
212 val = intel_de_read(dev_priv, PP_CONTROL(0)); in intel_lvds_pps_init_hw()
814 val = intel_de_read(i915, lvds_encoder->reg); in compute_is_dual_link_lvds()
865 lvds = intel_de_read(i915, lvds_reg); in intel_lvds_init()
H A Dintel_display_power.c1071 state = intel_de_read(dev_priv, reg) & DBUF_POWER_STATE; in gen9_dbuf_slice_set()
1179 u32 val = intel_de_read(dev_priv, LCPLL_CTL); in hsw_assert_cdclk()
1206 I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, HSW_PWR_WELL_CTL2), in assert_can_disable_lcpll()
1209 intel_de_read(dev_priv, SPLL_CTL) & SPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1212 intel_de_read(dev_priv, WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1215 intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, in assert_can_disable_lcpll()
1218 intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, in assert_can_disable_lcpll()
1221 intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1225 intel_de_read(dev_priv, HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, in assert_can_disable_lcpll()
1228 intel_de_read(dev_priv, BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, in assert_can_disable_lcpll()
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H A Dg4x_dp.c120 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED; in intel_dp_prepare()
170 bool cur_state = intel_de_read(dev_priv, intel_dp->output_reg) & DP_PORT_EN; in assert_dp_port()
181 bool cur_state = intel_de_read(dev_priv, DP_A) & DP_PLL_ENABLE; in assert_edp_pll()
255 u32 val = intel_de_read(dev_priv, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
279 val = intel_de_read(dev_priv, dp_reg); in g4x_dp_port_enabled()
346 tmp = intel_de_read(dev_priv, intel_dp->output_reg); in intel_dp_get_config()
351 u32 trans_dp = intel_de_read(dev_priv, in intel_dp_get_config()
392 if ((intel_de_read(dev_priv, DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) in intel_dp_get_config()
418 (intel_de_read(dev_priv, intel_dp->output_reg) & in intel_dp_link_down()
648 u32 dp_reg = intel_de_read(dev_priv, intel_dp->output_reg); in intel_enable_dp()
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H A Dintel_tv.c916 u32 tmp = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_hw_state()
1108 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_get_config()
1109 hctl1 = intel_de_read(dev_priv, TV_H_CTL_1); in intel_tv_get_config()
1110 hctl3 = intel_de_read(dev_priv, TV_H_CTL_3); in intel_tv_get_config()
1111 vctl1 = intel_de_read(dev_priv, TV_V_CTL_1); in intel_tv_get_config()
1112 vctl2 = intel_de_read(dev_priv, TV_V_CTL_2); in intel_tv_get_config()
1147 tmp = intel_de_read(dev_priv, TV_WIN_POS); in intel_tv_get_config()
1151 tmp = intel_de_read(dev_priv, TV_WIN_SIZE); in intel_tv_get_config()
1460 tv_ctl = intel_de_read(dev_priv, TV_CTL); in intel_tv_pre_enable()
1586 intel_de_read(dev_priv, TV_DAC) & TV_DAC_SAVE); in intel_tv_pre_enable()
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H A Dintel_dpio_phy.c293 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_levels()
297 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_levels()
303 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_levels()
314 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_levels()
319 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_levels()
331 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
334 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
342 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { in bxt_ddi_phy_is_enabled()
354 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); in bxt_get_grc()
498 val = intel_de_read(dev_priv, reg); in __phy_reg_verify_state()
[all …]
H A Dintel_hdmi.c76 intel_de_read(dev_priv, intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
85 intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & in assert_hdmi_transcoder_func_disabled()
207 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_write_infoframe()
249 *data++ = intel_de_read(dev_priv, VIDEO_DIP_DATA); in g4x_read_infoframe()
256 u32 val = intel_de_read(dev_priv, VIDEO_DIP_CTL); in g4x_infoframes_enabled()
277 u32 val = intel_de_read(dev_priv, reg); in ibx_write_infoframe()
321 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in ibx_read_infoframe()
330 u32 val = intel_de_read(dev_priv, reg); in ibx_infoframes_enabled()
352 u32 val = intel_de_read(dev_priv, reg); in cpt_write_infoframe()
399 *data++ = intel_de_read(dev_priv, TVIDEO_DIP_DATA(crtc->pipe)); in cpt_read_infoframe()
[all …]
H A Dintel_overlay.c330 tmp = intel_de_read(dev_priv, DOVSTA); in intel_overlay_continue()
464 if (!(intel_de_read(dev_priv, GEN2_ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT)) { in intel_overlay_release_old_vid()
944 u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
951 if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE) in update_pfit_vscale_ratio()
952 tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); in update_pfit_vscale_ratio()
954 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); in update_pfit_vscale_ratio()
1296 attrs->gamma0 = intel_de_read(dev_priv, OGAMC0); in intel_overlay_attrs_ioctl()
1297 attrs->gamma1 = intel_de_read(dev_priv, OGAMC1); in intel_overlay_attrs_ioctl()
1298 attrs->gamma2 = intel_de_read(dev_priv, OGAMC2); in intel_overlay_attrs_ioctl()
1299 attrs->gamma3 = intel_de_read(dev_priv, OGAMC3); in intel_overlay_attrs_ioctl()
[all …]
H A Dintel_dmc.c345 event_ctl = intel_de_read(i915, ctl_reg); in disable_flip_queue_event()
346 event_htp = intel_de_read(i915, htp_reg); in disable_flip_queue_event()
615 !intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), in assert_dmc_loaded()
617 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), in assert_dmc_loaded()
619 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), in assert_dmc_loaded()
1239 intel_de_read(i915, dc3co_reg)); in intel_dmc_debugfs_status_show()
1247 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); in intel_dmc_debugfs_status_show()
1250 intel_de_read(i915, dc6_reg)); in intel_dmc_debugfs_status_show()
1253 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); in intel_dmc_debugfs_status_show()
1257 intel_de_read(i915, DMC_SSP_BASE)); in intel_dmc_debugfs_status_show()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_suspend.c43 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
44 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
47 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
50 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
53 dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); in intel_save_swf()
54 dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); in intel_save_swf()
57 dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); in intel_save_swf()
95 dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); in i915_save_display()

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