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Searched refs:input_rate (Results 1 – 22 of 22) sorted by relevance

/openbmc/linux/drivers/clk/mmp/
H A Dclk-pll.c24 unsigned long input_rate; member
73 rate = pll->input_rate; in mmp_clk_pll_recalc_rate()
104 unsigned long input_rate, in mmp_clk_register_pll() argument
127 pll->input_rate = input_rate; in mmp_clk_register_pll()
159 clks[i].input_rate, in mmp_register_pll_clks()
H A Dclk.h235 unsigned long input_rate; member
/openbmc/u-boot/drivers/clk/aspeed/
H A Dclk_ast2400.c269 ulong input_rate; member
278 static bool ast2400_get_clock_config_default(ulong input_rate, in ast2400_get_clock_config_default() argument
287 if (default_cfg->input_rate == input_rate && in ast2400_get_clock_config_default()
307 static ulong ast2400_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2400_calc_clock_config() argument
314 const ulong input_rate_khz = input_rate / 1000; in ast2400_calc_clock_config()
324 if (ast2400_get_clock_config_default(input_rate, requested_rate, cfg)) in ast2400_calc_clock_config()
H A Dclk_ast2500.c243 ulong input_rate; member
252 static bool ast2500_get_clock_config_default(ulong input_rate, in ast2500_get_clock_config_default() argument
261 if (default_cfg->input_rate == input_rate && in ast2500_get_clock_config_default()
281 static ulong ast2500_calc_clock_config(ulong input_rate, ulong requested_rate, in ast2500_calc_clock_config() argument
288 const ulong input_rate_khz = input_rate / 1000; in ast2500_calc_clock_config()
298 if (ast2500_get_clock_config_default(input_rate, requested_rate, cfg)) in ast2500_calc_clock_config()
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h62 static inline u32 clk_get_divisor(ulong input_rate, uint output_rate) in clk_get_divisor() argument
66 clk_div = input_rate / output_rate; in clk_get_divisor()
/openbmc/linux/drivers/clk/tegra/
H A Dclk-pll.c526 for (sel = pll->params->freq_table; sel->input_rate != 0; sel++) in _get_table_rate()
527 if (sel->input_rate == parent_rate && in _get_table_rate()
531 if (sel->input_rate == 0) in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
959 unsigned long input_rate; in clk_plle_enable() local
966 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in clk_plle_enable()
968 if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) in clk_plle_enable()
1122 unsigned long flags = 0, input_rate; in clk_pllu_enable() local
1132 input_rate = clk_hw_get_rate(osc); in clk_pllu_enable()
1145 if (input_rate == utmi_parameters[i].osc_frequency) { in clk_pllu_enable()
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H A Dclk-tegra210.c1111 unsigned long input_rate; in pllx_get_dyn_steps() local
1115 input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); in pllx_get_dyn_steps()
1117 input_rate = 38400000; in pllx_get_dyn_steps()
1119 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); in pllx_get_dyn_steps()
1121 switch (input_rate) { in pllx_get_dyn_steps()
1138 __func__, input_rate); in pllx_get_dyn_steps()
1464 cfg->input_rate / cfg->m * cfg->n / in tegra210_pllx_dyn_ramp()
1480 unsigned long rate, unsigned long input_rate) in tegra210_pll_fixed_mdiv_cfg() argument
1501 cfg->m = tegra_pll_get_fixed_mdiv(hw, input_rate); in tegra210_pll_fixed_mdiv_cfg()
1510 cf = input_rate / cfg->m; in tegra210_pll_fixed_mdiv_cfg()
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H A Dclk.h165 unsigned long input_rate; member
907 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);
/openbmc/u-boot/drivers/spi/
H A Drk_spi.c48 uint input_rate; member
83 uint clk_div = DIV_ROUND_UP(priv->input_rate, speed); in rkspi_set_clk()
95 __func__, speed, priv->input_rate / clk_div); in rkspi_set_clk()
264 priv->input_rate = ret; in rockchip_spi_probe()
265 debug("%s: rate = %u\n", __func__, priv->input_rate); in rockchip_spi_probe()
/openbmc/u-boot/drivers/clk/rockchip/
H A Dclk_rk3036.c26 #define RATE_TO_DIV(input_rate, output_rate) \ argument
27 ((input_rate) / (output_rate) - 1);
29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3328.c28 #define RATE_TO_DIV(input_rate, output_rate) \ argument
29 ((input_rate) / (output_rate) - 1);
30 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3399.c40 #define RATE_TO_DIV(input_rate, output_rate) \ argument
41 ((input_rate) / (output_rate) - 1);
42 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk322x.c26 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3188.c71 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3128.c27 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3368.c41 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rv1108.c29 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
H A Dclk_rk3288.c131 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) argument
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c1408 unsigned int fine_scalar_bits, unsigned int input_rate, in clock_calc_best_scalar() argument
1417 debug("Input Rate is %u, Target is %u, Cap is %u\n", input_rate, in clock_calc_best_scalar()
1425 if (input_rate == 0 || target_rate == 0) in clock_calc_best_scalar()
1428 if (target_rate >= input_rate) in clock_calc_best_scalar()
1433 max(min(input_rate / i / target_rate, cap), 1U); in clock_calc_best_scalar()
1434 const unsigned int effective_rate = input_rate / i / in clock_calc_best_scalar()
/openbmc/linux/sound/pci/ctxfi/
H A Dctatc.c195 atc_get_pitch(unsigned int input_rate, unsigned int output_rate) in atc_get_pitch() argument
201 pitch = (input_rate / output_rate) << 24; in atc_get_pitch()
202 input_rate %= output_rate; in atc_get_pitch()
203 input_rate /= 100; in atc_get_pitch()
205 for (b = 31; ((b >= 0) && !(input_rate >> b)); ) in atc_get_pitch()
209 input_rate <<= (31 - b); in atc_get_pitch()
210 input_rate /= output_rate; in atc_get_pitch()
213 input_rate <<= b; in atc_get_pitch()
215 input_rate >>= -b; in atc_get_pitch()
217 pitch |= input_rate; in atc_get_pitch()
/openbmc/linux/sound/soc/stm/
H A Dstm32_i2s.c265 unsigned long input_rate, in stm32_i2s_calc_clk_div() argument
271 ratio = DIV_ROUND_CLOSEST(input_rate, output_rate); in stm32_i2s_calc_clk_div()
292 if (input_rate % divider) in stm32_i2s_calc_clk_div()
295 output_rate, input_rate / divider); in stm32_i2s_calc_clk_div()
H A Dstm32_sai_sub.c313 unsigned long input_rate, in stm32_sai_get_clk_div() argument
319 div = DIV_ROUND_CLOSEST(input_rate, output_rate); in stm32_sai_get_clk_div()
326 if (input_rate % div) in stm32_sai_get_clk_div()
329 output_rate, input_rate / div); in stm32_sai_get_clk_div()