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Searched refs:infracfg (Results 1 – 25 of 46) sorted by relevance

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/openbmc/linux/drivers/soc/mediatek/
H A Dmtk-infracfg.c28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
40 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
59 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
66 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
68 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
70 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_clear_bus_protection()
79 struct regmap *infracfg; in mtk_infracfg_init() local
87 infracfg = syscon_regmap_lookup_by_compatible("mediatek,mt8192-infracfg"); in mtk_infracfg_init()
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi284 infracfg: syscon@10001000 { label
285 compatible = "mediatek,mt8365-infracfg", "syscon";
329 clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
330 <&infracfg CLK_IFR_PMIC_AP>,
331 <&infracfg CLK_IFR_PWRAP_SYS>,
332 <&infracfg CLK_IFR_PWRAP_TMR>;
361 infracfg_nao: infracfg@1020e000 {
362 compatible = "mediatek,mt8365-infracfg", "syscon";
370 clocks = <&infracfg CLK_IFR_TRNG>;
389 clocks = <&infracfg CLK_IFR_AP_DMA>;
[all …]
H A Dmt7986a.dtsi143 infracfg: infracfg@10001000 { label
144 compatible = "mediatek,mt7986-infracfg", "syscon";
203 <&infracfg CLK_INFRA_PWM_STA>,
204 <&infracfg CLK_INFRA_PWM1_CK>,
205 <&infracfg CLK_INFRA_PWM2_CK>;
228 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
241 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
252 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
253 <&infracfg CLK_INFRA_UART0_CK>;
256 <&infracfg CLK_INFRA_UART0_SEL>;
[all …]
H A Dmt8183.dtsi742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
809 infracfg: syscon@10001000 { label
810 compatible = "mediatek,mt8183-infracfg", "syscon";
[all …]
H A Dmt8167.dtsi26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
54 mediatek,infracfg = <&infracfg>;
80 mediatek,infracfg = <&infracfg>;
91 mediatek,infracfg = <&infracfg>;
99 mediatek,infracfg = <&infracfg>;
H A Dmt8192.dtsi449 infracfg: syscon@10001000 { label
450 compatible = "mediatek,mt8192-infracfg", "syscon";
502 <&infracfg CLK_INFRA_AUDIO_26M_B>,
503 <&infracfg CLK_INFRA_AUDIO>;
505 mediatek,infracfg = <&infracfg>;
511 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
513 mediatek,infracfg = <&infracfg>;
528 mediatek,infracfg = <&infracfg>;
569 mediatek,infracfg = <&infracfg>;
583 mediatek,infracfg = <&infracfg>;
[all …]
H A Dmt7622.dtsi75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
213 infracfg: infracfg@10000000 { label
214 compatible = "mediatek,mt7622-infracfg",
225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
250 infracfg = <&infracfg>;
259 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
302 clocks = <&infracfg CLK_INFRA_TRNG>;
621 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
[all …]
H A Dmt6795.dtsi256 infracfg: syscon@10001000 { label
257 compatible = "mediatek,mt6795-infracfg", "syscon";
308 mediatek,infracfg = <&infracfg>;
341 mediatek,infracfg = <&infracfg>;
382 resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>;
408 clocks = <&infracfg CLK_INFRA_M4U>;
432 clocks = <&infracfg CLK_INFRA_GCE>;
707 clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>;
714 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>;
H A Dmt8173.dtsi159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
174 clocks = <&infracfg CLK_INFRA_CA53SEL>,
189 clocks = <&infracfg CLK_INFRA_CA72SEL>,
204 clocks = <&infracfg CLK_INFRA_CA72SEL>,
355 infracfg: power-controller@10001000 { label
356 compatible = "mediatek,mt8173-infracfg", "syscon";
481 mediatek,infracfg = <&infracfg>;
515 mediatek,infracfg = <&infracfg>;
533 clocks = <&infracfg CLK_INFRA_CLK_13M>,
542 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
[all …]
H A Dmt8516.dtsi57 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
70 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
83 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
96 clocks = <&infracfg CLK_IFR_MUX1_SEL>,
188 infracfg: infracfg@10001000 { label
189 compatible = "mediatek,mt8516-infracfg", "syscon";
H A Dmt2712e.dtsi252 infracfg: clock-controller@10001000 { label
253 compatible = "mediatek,mt2712-infracfg", "syscon";
293 infracfg = <&infracfg>;
319 clocks = <&infracfg CLK_INFRA_AO_SPI1>;
330 clocks = <&infracfg CLK_INFRA_M4U>;
332 mediatek,infracfg = <&infracfg>;
348 clocks = <&infracfg CLK_INFRA_M4U>;
350 mediatek,infracfg = <&infracfg>;
663 <&infracfg CLK_INFRA_AO_SPI0>;
/openbmc/u-boot/drivers/power/domain/
H A Dmtk-power-domain.c80 void __iomem *infracfg; member
167 static int mtk_infracfg_set_bus_protection(void __iomem *infracfg, in mtk_infracfg_set_bus_protection() argument
172 clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask); in mtk_infracfg_set_bus_protection()
174 return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val, in mtk_infracfg_set_bus_protection()
178 static int mtk_infracfg_clear_bus_protection(void __iomem *infracfg, in mtk_infracfg_clear_bus_protection() argument
183 clrbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask); in mtk_infracfg_clear_bus_protection()
185 return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val, in mtk_infracfg_clear_bus_protection()
249 ret = mtk_infracfg_clear_bus_protection(scpd->infracfg, in scpsys_power_on()
268 ret = mtk_infracfg_set_bus_protection(scpd->infracfg, in scpsys_power_off()
366 scpd->infracfg = regmap_get_range(regmap, 0); in mtk_power_domain_probe()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmt7623.dtsi31 clocks = <&infracfg CLK_INFRA_CPUSEL>,
41 clocks = <&infracfg CLK_INFRA_CPUSEL>,
51 clocks = <&infracfg CLK_INFRA_CPUSEL>,
61 clocks = <&infracfg CLK_INFRA_CPUSEL>,
106 infracfg: syscon@10001000 { label
107 compatible = "mediatek,mt7623-infracfg", "syscon";
134 infracfg = <&infracfg>;
H A Dmt7629.dtsi67 infracfg: syscon@10000000 { label
68 compatible = "mediatek,mt7629-infracfg", "syscon";
99 infracfg = <&infracfg>;
270 mediatek,infracfg = <&infracfg>;
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Dsoc.c23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init()
24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init()
26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
/openbmc/linux/Documentation/devicetree/bindings/soc/mediatek/
H A Dscpsys.txt32 - infracfg: must contain a phandle to the infracfg controller
65 infracfg = <&infracfg>;
/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dcpufreq-mediatek.txt70 clocks = <&infracfg CLK_INFRA_CPUSEL>,
192 clocks = <&infracfg CLK_INFRA_CA53SEL>,
204 clocks = <&infracfg CLK_INFRA_CA53SEL>,
216 clocks = <&infracfg CLK_INFRA_CA72SEL>,
228 clocks = <&infracfg CLK_INFRA_CA72SEL>,
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dmtk-btcvsd-snd.txt7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
/openbmc/linux/arch/arm/boot/dts/mediatek/
H A Dmt7629.dtsi81 infracfg: syscon@10000000 { label
82 compatible = "mediatek,mt7629-infracfg", "syscon";
102 infracfg = <&infracfg>;
133 clocks = <&infracfg CLK_INFRA_TRNG_PD>;
473 mediatek,infracfg = <&infracfg>;
H A Dmt7623.dtsi80 clocks = <&infracfg CLK_INFRA_CPUSEL>,
92 clocks = <&infracfg CLK_INFRA_CPUSEL>,
104 clocks = <&infracfg CLK_INFRA_CPUSEL>,
116 clocks = <&infracfg CLK_INFRA_CPUSEL>,
234 infracfg: syscon@10001000 { label
235 compatible = "mediatek,mt7623-infracfg",
236 "mediatek,mt2701-infracfg",
276 infracfg = <&infracfg>;
304 resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
306 clocks = <&infracfg CLK_INFRA_PMICSPI>,
[all …]
H A Dmt8135.dtsi133 infracfg: infracfg@10001000 { label
136 compatible = "mediatek,mt8135-infracfg", "syscon";
184 resets = <&infracfg MT8135_INFRA_PMIC_WRAP_RST>,
H A Dmt7623n.dtsi108 clocks = <&infracfg CLK_INFRA_M4U>;
132 clocks = <&infracfg CLK_INFRA_SMI>,
134 <&infracfg CLK_INFRA_SMI>;
259 clocks = <&infracfg CLK_INFRA_CEC>;
H A Dmt2701.dtsi132 infracfg: syscon@10001000 { label
133 compatible = "mediatek,mt2701-infracfg", "syscon";
155 infracfg = <&infracfg>;
192 clocks = <&infracfg CLK_INFRA_SMI>,
194 <&infracfg CLK_INFRA_SMI>;
222 clocks = <&infracfg CLK_INFRA_M4U>;
434 clocks = <&infracfg CLK_INFRA_AUDIO>,
/openbmc/linux/drivers/clk/mediatek/
H A DMakefile21 obj-$(CONFIG_COMMON_CLK_MT6795) += clk-mt6795-apmixedsys.o clk-mt6795-infracfg.o \
50 clk-mt7622-infracfg.o
59 obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o
63 obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
72 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173-apmixedsys.o clk-mt8173-infracfg.o \
/openbmc/linux/drivers/pmdomain/mediatek/
H A Dmtk-pm-domains.c47 struct regmap *infracfg; member
150 ret = _scpsys_bus_protect_enable(pd->data->bp_infracfg, pd->infracfg); in scpsys_bus_protect_enable()
194 return _scpsys_bus_protect_disable(pd->data->bp_infracfg, pd->infracfg); in scpsys_bus_protect_disable()
364 pd->infracfg = syscon_regmap_lookup_by_phandle_optional(node, "mediatek,infracfg"); in scpsys_add_one_domain()
365 if (IS_ERR(pd->infracfg)) in scpsys_add_one_domain()
366 return ERR_CAST(pd->infracfg); in scpsys_add_one_domain()

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