1*425da20aSKaiChieh ChuangMediatek ALSA BT SCO CVSD/MSBC Driver 2*425da20aSKaiChieh Chuang 3*425da20aSKaiChieh ChuangRequired properties: 4*425da20aSKaiChieh Chuang- compatible = "mediatek,mtk-btcvsd-snd"; 5*425da20aSKaiChieh Chuang- reg: register location and size of PKV and SRAM_BANK2 6*425da20aSKaiChieh Chuang- interrupts: should contain BTSCO interrupt 7*425da20aSKaiChieh Chuang- mediatek,infracfg: the phandles of INFRASYS 8*425da20aSKaiChieh Chuang- mediatek,offset: Array contains of register offset and mask 9*425da20aSKaiChieh Chuang infra_misc_offset, 10*425da20aSKaiChieh Chuang infra_conn_bt_cvsd_mask, 11*425da20aSKaiChieh Chuang cvsd_mcu_read_offset, 12*425da20aSKaiChieh Chuang cvsd_mcu_write_offset, 13*425da20aSKaiChieh Chuang cvsd_packet_indicator_offset 14*425da20aSKaiChieh Chuang 15*425da20aSKaiChieh ChuangExample: 16*425da20aSKaiChieh Chuang 17*425da20aSKaiChieh Chuang mtk-btcvsd-snd@18000000 { 18*425da20aSKaiChieh Chuang compatible = "mediatek,mtk-btcvsd-snd"; 19*425da20aSKaiChieh Chuang reg=<0 0x18000000 0 0x1000>, 20*425da20aSKaiChieh Chuang <0 0x18080000 0 0x8000>; 21*425da20aSKaiChieh Chuang interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 22*425da20aSKaiChieh Chuang mediatek,infracfg = <&infrasys>; 23*425da20aSKaiChieh Chuang mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; 24*425da20aSKaiChieh Chuang }; 25