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Searched refs:idc (Results 1 – 12 of 12) sorted by relevance

/openbmc/qemu/hw/intc/
H A Driscv_aplic.c441 static uint32_t riscv_aplic_idc_topi(RISCVAPLICState *aplic, uint32_t idc) in riscv_aplic_idc_topi() argument
446 if (aplic->num_harts <= idc) { in riscv_aplic_idc_topi()
450 ithres = aplic->ithreshold[idc]; in riscv_aplic_idc_topi()
460 if (ihartidx != idc) { in riscv_aplic_idc_topi()
482 static void riscv_aplic_idc_update(RISCVAPLICState *aplic, uint32_t idc) in riscv_aplic_idc_update() argument
486 if (aplic->msimode || aplic->num_harts <= idc) { in riscv_aplic_idc_update()
490 topi = riscv_aplic_idc_topi(aplic, idc); in riscv_aplic_idc_update()
492 aplic->idelivery[idc] && in riscv_aplic_idc_update()
493 (aplic->iforce[idc] || topi)) { in riscv_aplic_idc_update()
494 qemu_irq_raise(aplic->external_irqs[idc]); in riscv_aplic_idc_update()
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/openbmc/linux/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_83xx_vnic.c33 ahw->idc.vnic_state = QLCNIC_DEV_NPAR_NON_OPER; in qlcnic_83xx_disable_vnic_mode()
208 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; in qlcnic_83xx_config_vnic_opmode()
213 ahw->idc.state_entry = qlcnic_83xx_idc_vnic_pf_entry; in qlcnic_83xx_config_vnic_opmode()
218 ahw->idc.state_entry = qlcnic_83xx_idc_ready_state_entry; in qlcnic_83xx_config_vnic_opmode()
235 ahw->idc.vnic_state = QLCNIC_DEV_NPAR_NON_OPER; in qlcnic_83xx_config_vnic_opmode()
236 ahw->idc.vnic_wait_limit = QLCNIC_DEV_NPAR_OPER_TIMEO; in qlcnic_83xx_config_vnic_opmode()
244 struct qlc_83xx_idc *idc = &ahw->idc; in qlcnic_83xx_check_vnic_state() local
248 while (state != QLCNIC_DEV_NPAR_OPER && idc->vnic_wait_limit) { in qlcnic_83xx_check_vnic_state()
249 idc->vnic_wait_limit--; in qlcnic_83xx_check_vnic_state()
H A Dqlcnic_83xx_init.c146 cur = adapter->ahw->idc.curr_state; in qlcnic_83xx_idc_log_state_history()
147 prev = adapter->ahw->idc.prev_state; in qlcnic_83xx_idc_log_state_history()
151 adapter->ahw->idc.name[cur], in qlcnic_83xx_idc_log_state_history()
152 adapter->ahw->idc.name[prev]); in qlcnic_83xx_idc_log_state_history()
170 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; in qlcnic_83xx_idc_update_audit_reg()
176 adapter->ahw->idc.sec_counter = jiffies / HZ; in qlcnic_83xx_idc_update_audit_reg()
310 seconds = jiffies / HZ - adapter->ahw->idc.sec_counter; in qlcnic_83xx_idc_check_timeout()
652 set_bit(QLC_83XX_MODULE_LOADED, &adapter->ahw->idc.status); in qlcnic_83xx_idc_update_idc_params()
654 ahw->idc.quiesce_req = 0; in qlcnic_83xx_idc_update_idc_params()
655 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; in qlcnic_83xx_idc_update_idc_params()
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H A Dqlcnic_sriov_common.c584 adapter->ahw->idc.delay); in qlcnic_sriov_setup_vf()
623 set_bit(QLC_83XX_MODULE_LOADED, &ahw->idc.status); in qlcnic_sriov_vf_init()
624 ahw->idc.delay = QLC_83XX_IDC_FW_POLL_DELAY; in qlcnic_sriov_vf_init()
1742 struct qlc_83xx_idc *idc = &ahw->idc; in qlcnic_sriov_vf_handle_dev_ready() local
1746 if ((idc->prev_state == QLC_83XX_IDC_DEV_NEED_RESET) || in qlcnic_sriov_vf_handle_dev_ready()
1747 (idc->prev_state == QLC_83XX_IDC_DEV_INIT)) { in qlcnic_sriov_vf_handle_dev_ready()
1772 struct qlc_83xx_idc *idc = &ahw->idc; in qlcnic_sriov_vf_handle_context_reset() local
1791 clear_bit(QLC_83XX_MODULE_LOADED, &idc->status); in qlcnic_sriov_vf_handle_context_reset()
1831 if (ahw->idc.prev_state != QLC_83XX_IDC_DEV_READY) in qlcnic_sriov_vf_idc_ready_state()
1842 struct qlc_83xx_idc *idc = &adapter->ahw->idc; in qlcnic_sriov_vf_idc_failed_state() local
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H A Dqlcnic_83xx_hw.c959 clear_bit(QLC_83XX_IDC_COMP_AEN, &adapter->ahw->idc.status); in qlcnic_83xx_handle_idc_comp_aen()
1867 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); in qlcnic_83xx_set_lb_mode()
1880 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); in qlcnic_83xx_set_lb_mode()
1891 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); in qlcnic_83xx_set_lb_mode()
1902 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); in qlcnic_83xx_set_lb_mode()
1906 } while (test_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status)); in qlcnic_83xx_set_lb_mode()
1922 set_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); in qlcnic_83xx_clear_lb_mode()
1934 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); in qlcnic_83xx_clear_lb_mode()
1945 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); in qlcnic_83xx_clear_lb_mode()
1956 clear_bit(QLC_83XX_IDC_COMP_AEN, &ahw->idc.status); in qlcnic_83xx_clear_lb_mode()
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H A Dqlcnic.h526 struct qlc_83xx_idc idc; member
/openbmc/qemu/hw/dma/
H A Di8257.c599 IsaDmaClass *idc = ISADMA_CLASS(klass); in i8257_class_init() local
606 idc->has_autoinitialization = i8257_dma_has_autoinitialization; in i8257_class_init()
607 idc->read_memory = i8257_dma_read_memory; in i8257_class_init()
608 idc->write_memory = i8257_dma_write_memory; in i8257_class_init()
609 idc->hold_DREQ = i8257_dma_hold_DREQ; in i8257_class_init()
610 idc->release_DREQ = i8257_dma_release_DREQ; in i8257_class_init()
611 idc->schedule = i8257_dma_schedule; in i8257_class_init()
612 idc->register_channel = i8257_dma_register_channel; in i8257_class_init()
/openbmc/linux/drivers/media/platform/amphion/
H A Dvpu_codec.h42 u32 idc; member
H A Dvpu_windsor.c1062 if (params->sar.idc == V4L2_MPEG_VIDEO_H264_VUI_SAR_IDC_EXTENDED) in vpu_windsor_set_sar()
1065 expert->config_param.aspect_ratio = params->sar.idc; in vpu_windsor_set_sar()
H A Dvenc.c567 venc->params.sar.idc = ctrl->val; in venc_op_s_ctrl()
1211 venc->params.sar.idc, in venc_get_debug_info()
/openbmc/linux/arch/arm64/kvm/
H A Dsys_regs.c1766 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val)); in set_clidr() local
1768 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc)) in set_clidr()
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-codec.rst739 .. _v4l2-mpeg-video-h264-vui-sar-idc: