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Searched refs:flushing (Results 1 – 25 of 76) sorted by relevance

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/openbmc/linux/Documentation/admin-guide/hw-vuln/
H A Dl1tf.rst148 'L1D vulnerable' L1D flushing is disabled
191 The conditional mode avoids L1D flushing after VMEXITs which execute
373 the hypervisors, i.e. unconditional L1D flushing
386 mitigation, i.e. conditional L1D flushing
395 i.e. conditional L1D flushing.
413 The default is 'flush'. For details about L1D flushing see :ref:`l1d_flush`.
421 The KVM hypervisor mitigation mechanism, flushing the L1D cache when
466 To avoid the overhead of the default L1D flushing on VMENTER the
467 administrator can disable the flushing via the kernel command line and
479 the kernel, it's only required to enforce L1D flushing on VMENTER.
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H A Dl1d_flush.rst38 If the underlying CPU supports L1D flushing in hardware, the hardware
66 **NOTE** : The opt-in of a task for L1D flushing works only when the task's
68 requested L1D flushing is scheduled on a SMT-enabled core the kernel sends
/openbmc/linux/drivers/accessibility/speakup/
H A Dsynth.c41 .flushing = 0,
78 if (speakup_info.flushing) { in _spk_do_catch_up()
79 speakup_info.flushing = 0; in _spk_do_catch_up()
199 speakup_info.flushing = 1; in spk_do_flush()
H A Dspeakup_soft.c240 if (!synth_buffer_empty() || speakup_info.flushing) in softsynthx_read()
264 if (speakup_info.flushing) { in softsynthx_read()
265 speakup_info.flushing = 0; in softsynthx_read()
361 (!synth_buffer_empty() || speakup_info.flushing)) in softsynth_poll()
H A Dthread.c35 (speakup_info.flushing || in speakup_thread()
H A Dspeakup_apollo.c163 if (speakup_info.flushing) { in do_catch_up()
164 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_decext.c174 if (speakup_info.flushing) { in do_catch_up()
175 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_keypc.c196 if (speakup_info.flushing) { in do_catch_up()
197 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_acntpc.c195 if (speakup_info.flushing) { in do_catch_up()
196 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_dectlk.c249 if (speakup_info.flushing) { in do_catch_up()
250 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_decpc.c394 if (speakup_info.flushing) { in do_catch_up()
395 speakup_info.flushing = 0; in do_catch_up()
H A Dspeakup_dtlk.c209 if (speakup_info.flushing) { in do_catch_up()
210 speakup_info.flushing = 0; in do_catch_up()
/openbmc/linux/Documentation/core-api/
H A Dcachetlb.rst7 This document describes the cache/tlb flushing interfaces called
17 thinking SMP cache/tlb flushing must be so inefficient, this is in
23 First, the TLB flushing interfaces, since they are the simplest. The
56 Here we are flushing a specific range of (user) virtual
108 Next, we have the cache flushing interfaces. In general, when Linux
130 The cache flushing routines below need only deal with cache flushing
165 Here we are flushing a specific range of (user) virtual
215 Here in these two interfaces we are flushing a specific range
343 Any necessary cache flushing or other coherency operations
380 coherency. It must do this by flushing the vmap range before doing
/openbmc/linux/drivers/infiniband/hw/mlx4/
H A Dmcg.c686 } else if (method == IB_SA_METHOD_DELETE_RESP && group->demux->flushing) in mlx4_ib_mcg_work_handler()
941 if (ctx->flushing) in mlx4_ib_mcg_multiplex_handler()
1065 ctx->flushing = 0; in mlx4_ib_mcg_port_init()
1134 cw->ctx->flushing = 0; in mcg_clean_task()
1142 if (ctx->flushing) in mlx4_ib_mcg_port_cleanup()
1145 ctx->flushing = 1; in mlx4_ib_mcg_port_cleanup()
1149 ctx->flushing = 0; in mlx4_ib_mcg_port_cleanup()
1155 ctx->flushing = 0; in mlx4_ib_mcg_port_cleanup()
/openbmc/linux/Documentation/arch/x86/
H A Dpti.rst96 allows us to skip flushing the entire TLB when switching page
119 h. INVPCID is a TLB-flushing instruction which allows flushing
123 flushing a kernel address, we need to flush all PCIDs, so a
124 single kernel address flush will require a TLB-flushing CR3
/openbmc/linux/Documentation/ABI/testing/
H A Dprocfs-diskstats40 20 time spent flushing
/openbmc/qemu/include/hw/audio/
H A Dvirtio-snd.h145 bool flushing; member
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/mozjs/mozjs-128/
H A Darmv5.patch27 // We assume the icache flushing routines on other platforms take care of this
/openbmc/linux/drivers/char/xillybus/
H A Dxillyusb.c142 unsigned int flushing; member
916 chan->flushing = 0; in process_in_opcode()
1140 if (chan->flushing) { in flush_downstream()
1169 chan->flushing = 1; in flush_downstream()
1187 while (chan->flushing) { in flush_downstream()
1189 !chan->flushing || in flush_downstream()
1201 while (chan->flushing) { in flush_downstream()
1208 !chan->flushing || in flush_downstream()
/openbmc/linux/Documentation/block/
H A Dwriteback_cache_control.rst45 worry if the underlying devices need any explicit cache flushing and how
71 driver needs to tell the block layer that it supports flushing caches by
/openbmc/linux/fs/xfs/
H A Dxfs_trans_ail.c428 int flushing = 0; in xfsaild_push() local
510 flushing++; in xfsaild_push()
571 } else if (((stuck + flushing) * 100) / count > 90) { in xfsaild_push()
/openbmc/linux/include/trace/events/
H A Djbd2.h261 __field( unsigned long, flushing )
275 __entry->flushing = stats->rs_flushing;
290 jiffies_to_msecs(__entry->flushing),
/openbmc/linux/fs/ceph/
H A Dcaps.c1372 int flushing, u64 flush_tid, u64 oldest_flush_tid) in __prep_cap() argument
1405 arg->follows = flushing ? ci->i_head_snapc->seq : 0; in __prep_cap()
1418 if (flushing & CEPH_CAP_XATTR_EXCL) { in __prep_cap()
1436 arg->dirty = flushing; in __prep_cap()
1883 int flushing; in __mark_caps_flushing() local
1890 flushing = ci->i_dirty_caps; in __mark_caps_flushing()
1892 ceph_cap_string(flushing), in __mark_caps_flushing()
1894 ceph_cap_string(ci->i_flushing_caps | flushing)); in __mark_caps_flushing()
1895 ci->i_flushing_caps |= flushing; in __mark_caps_flushing()
1900 cf->caps = flushing; in __mark_caps_flushing()
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/openbmc/u-boot/doc/
H A DREADME.mips29 2) fix dcache_disable() to do both flushing and disabling cache.
/openbmc/linux/Documentation/networking/devlink/
H A Dmlx5.rst145 Recover by flushing the tx queue and reset it.
148 Recover by flushing and re-creating all PTP channels.
178 Recover (if needed) by flushing the related queue and reset it.

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