xref: /openbmc/linux/drivers/accessibility/speakup/speakup_decpc.c (revision 7ae9fb1b7ecbb5d85d07857943f677fd1a559b18)
12067fd92SSamuel Thibault // SPDX-License-Identifier: GPL-2.0+
22067fd92SSamuel Thibault /*
32067fd92SSamuel Thibault  * This is the DECtalk PC speakup driver
42067fd92SSamuel Thibault  *
52067fd92SSamuel Thibault  * Some constants from DEC's DOS driver:
62067fd92SSamuel Thibault  *      Copyright (c) by Digital Equipment Corp.
72067fd92SSamuel Thibault  *
82067fd92SSamuel Thibault  * 386BSD DECtalk PC driver:
92067fd92SSamuel Thibault  *      Copyright (c) 1996 Brian Buhrow <buhrow@lothlorien.nfbcal.org>
102067fd92SSamuel Thibault  *
112067fd92SSamuel Thibault  * Linux DECtalk PC driver:
122067fd92SSamuel Thibault  *      Copyright (c) 1997 Nicolas Pitre <nico@cam.org>
132067fd92SSamuel Thibault  *
142067fd92SSamuel Thibault  * speakup DECtalk PC Internal driver:
152067fd92SSamuel Thibault  *      Copyright (c) 2003 David Borowski <david575@golden.net>
162067fd92SSamuel Thibault  *
172067fd92SSamuel Thibault  * All rights reserved.
182067fd92SSamuel Thibault  */
192067fd92SSamuel Thibault #include <linux/jiffies.h>
202067fd92SSamuel Thibault #include <linux/sched.h>
212067fd92SSamuel Thibault #include <linux/timer.h>
222067fd92SSamuel Thibault #include <linux/kthread.h>
232067fd92SSamuel Thibault 
242067fd92SSamuel Thibault #include "spk_priv.h"
252067fd92SSamuel Thibault #include "speakup.h"
262067fd92SSamuel Thibault 
272067fd92SSamuel Thibault #define	MODULE_init		0x0dec	/* module in boot code */
282067fd92SSamuel Thibault #define	MODULE_self_test	0x8800	/* module in self-test */
292067fd92SSamuel Thibault #define	MODULE_reset		0xffff	/* reinit the whole module */
302067fd92SSamuel Thibault 
312067fd92SSamuel Thibault #define	MODE_mask		0xf000	/* mode bits in high nibble */
322067fd92SSamuel Thibault #define	MODE_null		0x0000
332067fd92SSamuel Thibault #define	MODE_test		0x2000	/* in testing mode */
342067fd92SSamuel Thibault #define	MODE_status		0x8000
352067fd92SSamuel Thibault #define	STAT_int		0x0001	/* running in interrupt mode */
362067fd92SSamuel Thibault #define	STAT_tr_char		0x0002	/* character data to transmit */
372067fd92SSamuel Thibault #define	STAT_rr_char		0x0004	/* ready to receive char data */
382067fd92SSamuel Thibault #define	STAT_cmd_ready		0x0008	/* ready to accept commands */
392067fd92SSamuel Thibault #define	STAT_dma_ready		0x0010	/* dma command ready */
402067fd92SSamuel Thibault #define	STAT_digitized		0x0020	/* spc in digitized mode */
412067fd92SSamuel Thibault #define	STAT_new_index		0x0040	/* new last index ready */
422067fd92SSamuel Thibault #define	STAT_new_status		0x0080	/* new status posted */
432067fd92SSamuel Thibault #define	STAT_dma_state		0x0100	/* dma state toggle */
442067fd92SSamuel Thibault #define	STAT_index_valid	0x0200	/* indexs are valid */
452067fd92SSamuel Thibault #define	STAT_flushing		0x0400	/* flush in progress */
462067fd92SSamuel Thibault #define	STAT_self_test		0x0800	/* module in self test */
472067fd92SSamuel Thibault #define	MODE_ready		0xc000	/* module ready for next phase */
482067fd92SSamuel Thibault #define	READY_boot		0x0000
492067fd92SSamuel Thibault #define	READY_kernel		0x0001
502067fd92SSamuel Thibault #define	MODE_error		0xf000
512067fd92SSamuel Thibault 
522067fd92SSamuel Thibault #define	CMD_mask		0xf000	/* mask for command nibble */
532067fd92SSamuel Thibault #define	CMD_null		0x0000	/* post status */
542067fd92SSamuel Thibault #define	CMD_control		0x1000	/* hard control command */
552067fd92SSamuel Thibault #define	CTRL_mask		0x0F00	/* mask off control nibble */
562067fd92SSamuel Thibault #define	CTRL_data		0x00FF	/* mask to get data byte */
572067fd92SSamuel Thibault #define	CTRL_null		0x0000	/* null control */
582067fd92SSamuel Thibault #define	CTRL_vol_up		0x0100	/* increase volume */
592067fd92SSamuel Thibault #define	CTRL_vol_down		0x0200	/* decrease volume */
602067fd92SSamuel Thibault #define	CTRL_vol_set		0x0300	/* set volume */
612067fd92SSamuel Thibault #define	CTRL_pause		0x0400	/* pause spc */
622067fd92SSamuel Thibault #define	CTRL_resume		0x0500	/* resume spc clock */
632067fd92SSamuel Thibault #define	CTRL_resume_spc		0x0001	/* resume spc soft pause */
642067fd92SSamuel Thibault #define	CTRL_flush		0x0600	/* flush all buffers */
652067fd92SSamuel Thibault #define	CTRL_int_enable		0x0700	/* enable status change ints */
662067fd92SSamuel Thibault #define	CTRL_buff_free		0x0800	/* buffer remain count */
672067fd92SSamuel Thibault #define	CTRL_buff_used		0x0900	/* buffer in use */
682067fd92SSamuel Thibault #define	CTRL_speech		0x0a00	/* immediate speech change */
692067fd92SSamuel Thibault #define	CTRL_SP_voice		0x0001	/* voice change */
702067fd92SSamuel Thibault #define	CTRL_SP_rate		0x0002	/* rate change */
712067fd92SSamuel Thibault #define	CTRL_SP_comma		0x0003	/* comma pause change */
722067fd92SSamuel Thibault #define	CTRL_SP_period		0x0004	/* period pause change */
732067fd92SSamuel Thibault #define	CTRL_SP_rate_delta	0x0005	/* delta rate change */
742067fd92SSamuel Thibault #define	CTRL_SP_get_param	0x0006	/* return the desired parameter */
752067fd92SSamuel Thibault #define	CTRL_last_index		0x0b00	/* get last index spoken */
762067fd92SSamuel Thibault #define	CTRL_io_priority	0x0c00	/* change i/o priority */
772067fd92SSamuel Thibault #define	CTRL_free_mem		0x0d00	/* get free paragraphs on module */
782067fd92SSamuel Thibault #define	CTRL_get_lang		0x0e00	/* return bitmask of loaded languages */
792067fd92SSamuel Thibault #define	CMD_test		0x2000	/* self-test request */
802067fd92SSamuel Thibault #define	TEST_mask		0x0F00	/* isolate test field */
812067fd92SSamuel Thibault #define	TEST_null		0x0000	/* no test requested */
822067fd92SSamuel Thibault #define	TEST_isa_int		0x0100	/* assert isa irq */
832067fd92SSamuel Thibault #define	TEST_echo		0x0200	/* make data in == data out */
842067fd92SSamuel Thibault #define	TEST_seg		0x0300	/* set peek/poke segment */
852067fd92SSamuel Thibault #define	TEST_off		0x0400	/* set peek/poke offset */
862067fd92SSamuel Thibault #define	TEST_peek		0x0500	/* data out == *peek */
872067fd92SSamuel Thibault #define	TEST_poke		0x0600	/* *peek == data in */
882067fd92SSamuel Thibault #define	TEST_sub_code		0x00FF	/* user defined test sub codes */
892067fd92SSamuel Thibault #define	CMD_id			0x3000	/* return software id */
902067fd92SSamuel Thibault #define	ID_null			0x0000	/* null id */
912067fd92SSamuel Thibault #define	ID_kernel		0x0100	/* kernel code executing */
922067fd92SSamuel Thibault #define	ID_boot			0x0200	/* boot code executing */
932067fd92SSamuel Thibault #define	CMD_dma			0x4000	/* force a dma start */
942067fd92SSamuel Thibault #define	CMD_reset		0x5000	/* reset module status */
952067fd92SSamuel Thibault #define	CMD_sync		0x6000	/* kernel sync command */
962067fd92SSamuel Thibault #define	CMD_char_in		0x7000	/* single character send */
972067fd92SSamuel Thibault #define	CMD_char_out		0x8000	/* single character get */
982067fd92SSamuel Thibault #define	CHAR_count_1		0x0100	/* one char in cmd_low */
992067fd92SSamuel Thibault #define	CHAR_count_2		0x0200	/* the second in data_low */
1002067fd92SSamuel Thibault #define	CHAR_count_3		0x0300	/* the third in data_high */
1012067fd92SSamuel Thibault #define	CMD_spc_mode		0x9000	/* change spc mode */
1022067fd92SSamuel Thibault #define	CMD_spc_to_text		0x0100	/* set to text mode */
1032067fd92SSamuel Thibault #define	CMD_spc_to_digit	0x0200	/* set to digital mode */
1042067fd92SSamuel Thibault #define	CMD_spc_rate		0x0400	/* change spc data rate */
1052067fd92SSamuel Thibault #define	CMD_error		0xf000	/* severe error */
1062067fd92SSamuel Thibault 
1072067fd92SSamuel Thibault enum {	PRIMARY_DIC	= 0, USER_DIC, COMMAND_DIC, ABBREV_DIC };
1082067fd92SSamuel Thibault 
1092067fd92SSamuel Thibault #define	DMA_single_in		0x01
1102067fd92SSamuel Thibault #define	DMA_single_out		0x02
1112067fd92SSamuel Thibault #define	DMA_buff_in		0x03
1122067fd92SSamuel Thibault #define	DMA_buff_out		0x04
1132067fd92SSamuel Thibault #define	DMA_control		0x05
1142067fd92SSamuel Thibault #define	DT_MEM_ALLOC		0x03
1152067fd92SSamuel Thibault #define	DT_SET_DIC		0x04
1162067fd92SSamuel Thibault #define	DT_START_TASK		0x05
1172067fd92SSamuel Thibault #define	DT_LOAD_MEM		0x06
1182067fd92SSamuel Thibault #define	DT_READ_MEM		0x07
1192067fd92SSamuel Thibault #define	DT_DIGITAL_IN		0x08
1202067fd92SSamuel Thibault #define	DMA_sync		0x06
1212067fd92SSamuel Thibault #define	DMA_sync_char		0x07
1222067fd92SSamuel Thibault 
1232067fd92SSamuel Thibault #define DRV_VERSION "2.12"
1242067fd92SSamuel Thibault #define PROCSPEECH 0x0b
1252067fd92SSamuel Thibault #define SYNTH_IO_EXTENT 8
1262067fd92SSamuel Thibault 
1272067fd92SSamuel Thibault static int synth_probe(struct spk_synth *synth);
1281941ab1dSSamuel Thibault static void dtpc_release(struct spk_synth *synth);
1292067fd92SSamuel Thibault static const char *synth_immediate(struct spk_synth *synth, const char *buf);
1302067fd92SSamuel Thibault static void do_catch_up(struct spk_synth *synth);
1312067fd92SSamuel Thibault static void synth_flush(struct spk_synth *synth);
1322067fd92SSamuel Thibault 
1332067fd92SSamuel Thibault static int synth_portlist[] = { 0x340, 0x350, 0x240, 0x250, 0 };
1342067fd92SSamuel Thibault static int in_escape, is_flushing;
1352067fd92SSamuel Thibault static int dt_stat, dma_state;
1362067fd92SSamuel Thibault 
137*b75cfeb1SOsama Muhammad 
138*b75cfeb1SOsama Muhammad enum default_vars_id {
139*b75cfeb1SOsama Muhammad 	CAPS_START_ID = 0, CAPS_STOP_ID,
140*b75cfeb1SOsama Muhammad 	RATE_ID, PITCH_ID, INFLECTION_ID,
141*b75cfeb1SOsama Muhammad 	VOL_ID, PUNCT_ID, VOICE_ID,
142*b75cfeb1SOsama Muhammad 	DIRECT_ID, V_LAST_VAR_ID,
143*b75cfeb1SOsama Muhammad 	NB_ID,
144*b75cfeb1SOsama Muhammad };
145*b75cfeb1SOsama Muhammad 
146*b75cfeb1SOsama Muhammad 
147*b75cfeb1SOsama Muhammad 
148*b75cfeb1SOsama Muhammad static struct var_t vars[NB_ID] = {
149*b75cfeb1SOsama Muhammad 	[CAPS_START_ID] = { CAPS_START, .u.s = {"[:dv ap 200]" } },
150*b75cfeb1SOsama Muhammad 	[CAPS_STOP_ID] = { CAPS_STOP, .u.s = {"[:dv ap 100]" } },
151*b75cfeb1SOsama Muhammad 	[RATE_ID] = { RATE, .u.n = {"[:ra %d]", 9, 0, 18, 150, 25, NULL } },
152*b75cfeb1SOsama Muhammad 	[PITCH_ID] = { PITCH, .u.n = {"[:dv ap %d]", 80, 0, 100, 20, 0, NULL } },
153*b75cfeb1SOsama Muhammad 	[INFLECTION_ID] = { INFLECTION, .u.n = {"[:dv pr %d] ", 100, 0, 10000, 0, 0, NULL } },
154*b75cfeb1SOsama Muhammad 	[VOL_ID] = { VOL, .u.n = {"[:vo se %d]", 5, 0, 9, 5, 10, NULL } },
155*b75cfeb1SOsama Muhammad 	[PUNCT_ID] = { PUNCT, .u.n = {"[:pu %c]", 0, 0, 2, 0, 0, "nsa" } },
156*b75cfeb1SOsama Muhammad 	[VOICE_ID] = { VOICE, .u.n = {"[:n%c]", 0, 0, 9, 0, 0, "phfdburwkv" } },
157*b75cfeb1SOsama Muhammad 	[DIRECT_ID] = { DIRECT, .u.n = {NULL, 0, 0, 1, 0, 0, NULL } },
1582067fd92SSamuel Thibault 	V_LAST_VAR
1592067fd92SSamuel Thibault };
1602067fd92SSamuel Thibault 
1612067fd92SSamuel Thibault /*
1622067fd92SSamuel Thibault  * These attributes will appear in /sys/accessibility/speakup/decpc.
1632067fd92SSamuel Thibault  */
1642067fd92SSamuel Thibault static struct kobj_attribute caps_start_attribute =
1652067fd92SSamuel Thibault 	__ATTR(caps_start, 0644, spk_var_show, spk_var_store);
1662067fd92SSamuel Thibault static struct kobj_attribute caps_stop_attribute =
1672067fd92SSamuel Thibault 	__ATTR(caps_stop, 0644, spk_var_show, spk_var_store);
1682067fd92SSamuel Thibault static struct kobj_attribute pitch_attribute =
1692067fd92SSamuel Thibault 	__ATTR(pitch, 0644, spk_var_show, spk_var_store);
1702067fd92SSamuel Thibault static struct kobj_attribute inflection_attribute =
1712067fd92SSamuel Thibault 	__ATTR(inflection, 0644, spk_var_show, spk_var_store);
1722067fd92SSamuel Thibault static struct kobj_attribute punct_attribute =
1732067fd92SSamuel Thibault 	__ATTR(punct, 0644, spk_var_show, spk_var_store);
1742067fd92SSamuel Thibault static struct kobj_attribute rate_attribute =
1752067fd92SSamuel Thibault 	__ATTR(rate, 0644, spk_var_show, spk_var_store);
1762067fd92SSamuel Thibault static struct kobj_attribute voice_attribute =
1772067fd92SSamuel Thibault 	__ATTR(voice, 0644, spk_var_show, spk_var_store);
1782067fd92SSamuel Thibault static struct kobj_attribute vol_attribute =
1792067fd92SSamuel Thibault 	__ATTR(vol, 0644, spk_var_show, spk_var_store);
1802067fd92SSamuel Thibault 
1812067fd92SSamuel Thibault static struct kobj_attribute delay_time_attribute =
1822067fd92SSamuel Thibault 	__ATTR(delay_time, 0644, spk_var_show, spk_var_store);
1832067fd92SSamuel Thibault static struct kobj_attribute direct_attribute =
1842067fd92SSamuel Thibault 	__ATTR(direct, 0644, spk_var_show, spk_var_store);
1852067fd92SSamuel Thibault static struct kobj_attribute full_time_attribute =
1862067fd92SSamuel Thibault 	__ATTR(full_time, 0644, spk_var_show, spk_var_store);
1872067fd92SSamuel Thibault static struct kobj_attribute jiffy_delta_attribute =
1882067fd92SSamuel Thibault 	__ATTR(jiffy_delta, 0644, spk_var_show, spk_var_store);
1892067fd92SSamuel Thibault static struct kobj_attribute trigger_time_attribute =
1902067fd92SSamuel Thibault 	__ATTR(trigger_time, 0644, spk_var_show, spk_var_store);
1912067fd92SSamuel Thibault 
1922067fd92SSamuel Thibault /*
1932067fd92SSamuel Thibault  * Create a group of attributes so that we can create and destroy them all
1942067fd92SSamuel Thibault  * at once.
1952067fd92SSamuel Thibault  */
1962067fd92SSamuel Thibault static struct attribute *synth_attrs[] = {
1972067fd92SSamuel Thibault 	&caps_start_attribute.attr,
1982067fd92SSamuel Thibault 	&caps_stop_attribute.attr,
1992067fd92SSamuel Thibault 	&pitch_attribute.attr,
2002067fd92SSamuel Thibault 	&inflection_attribute.attr,
2012067fd92SSamuel Thibault 	&punct_attribute.attr,
2022067fd92SSamuel Thibault 	&rate_attribute.attr,
2032067fd92SSamuel Thibault 	&voice_attribute.attr,
2042067fd92SSamuel Thibault 	&vol_attribute.attr,
2052067fd92SSamuel Thibault 	&delay_time_attribute.attr,
2062067fd92SSamuel Thibault 	&direct_attribute.attr,
2072067fd92SSamuel Thibault 	&full_time_attribute.attr,
2082067fd92SSamuel Thibault 	&jiffy_delta_attribute.attr,
2092067fd92SSamuel Thibault 	&trigger_time_attribute.attr,
2102067fd92SSamuel Thibault 	NULL,	/* need to NULL terminate the list of attributes */
2112067fd92SSamuel Thibault };
2122067fd92SSamuel Thibault 
2132067fd92SSamuel Thibault static struct spk_synth synth_dec_pc = {
2142067fd92SSamuel Thibault 	.name = "decpc",
2152067fd92SSamuel Thibault 	.version = DRV_VERSION,
2162067fd92SSamuel Thibault 	.long_name = "Dectalk PC",
2172067fd92SSamuel Thibault 	.init = "[:pe -380]",
2182067fd92SSamuel Thibault 	.procspeech = PROCSPEECH,
2192067fd92SSamuel Thibault 	.delay = 500,
2202067fd92SSamuel Thibault 	.trigger = 50,
2212067fd92SSamuel Thibault 	.jiffies = 50,
2222067fd92SSamuel Thibault 	.full = 1000,
2232067fd92SSamuel Thibault 	.flags = SF_DEC,
2242067fd92SSamuel Thibault 	.startup = SYNTH_START,
2252067fd92SSamuel Thibault 	.checkval = SYNTH_CHECK,
2262067fd92SSamuel Thibault 	.vars = vars,
2272067fd92SSamuel Thibault 	.io_ops = &spk_serial_io_ops,
2282067fd92SSamuel Thibault 	.probe = synth_probe,
2292067fd92SSamuel Thibault 	.release = dtpc_release,
2302067fd92SSamuel Thibault 	.synth_immediate = synth_immediate,
2312067fd92SSamuel Thibault 	.catch_up = do_catch_up,
2322067fd92SSamuel Thibault 	.flush = synth_flush,
2332067fd92SSamuel Thibault 	.is_alive = spk_synth_is_alive_nop,
2342067fd92SSamuel Thibault 	.synth_adjust = NULL,
2352067fd92SSamuel Thibault 	.read_buff_add = NULL,
2362067fd92SSamuel Thibault 	.get_index = NULL,
2372067fd92SSamuel Thibault 	.indexing = {
2382067fd92SSamuel Thibault 		.command = NULL,
2392067fd92SSamuel Thibault 		.lowindex = 0,
2402067fd92SSamuel Thibault 		.highindex = 0,
2412067fd92SSamuel Thibault 		.currindex = 0,
2422067fd92SSamuel Thibault 	},
2432067fd92SSamuel Thibault 	.attributes = {
2442067fd92SSamuel Thibault 		.attrs = synth_attrs,
2452067fd92SSamuel Thibault 		.name = "decpc",
2462067fd92SSamuel Thibault 	},
2472067fd92SSamuel Thibault };
2482067fd92SSamuel Thibault 
dt_getstatus(void)2492067fd92SSamuel Thibault static int dt_getstatus(void)
2502067fd92SSamuel Thibault {
2512067fd92SSamuel Thibault 	dt_stat = inb_p(speakup_info.port_tts) |
2522067fd92SSamuel Thibault 		 (inb_p(speakup_info.port_tts + 1) << 8);
2532067fd92SSamuel Thibault 	return dt_stat;
2542067fd92SSamuel Thibault }
2552067fd92SSamuel Thibault 
dt_sendcmd(u_int cmd)2562067fd92SSamuel Thibault static void dt_sendcmd(u_int cmd)
2572067fd92SSamuel Thibault {
2582067fd92SSamuel Thibault 	outb_p(cmd & 0xFF, speakup_info.port_tts);
2592067fd92SSamuel Thibault 	outb_p((cmd >> 8) & 0xFF, speakup_info.port_tts + 1);
2602067fd92SSamuel Thibault }
2612067fd92SSamuel Thibault 
dt_waitbit(int bit)2622067fd92SSamuel Thibault static int dt_waitbit(int bit)
2632067fd92SSamuel Thibault {
2642067fd92SSamuel Thibault 	int timeout = 100;
2652067fd92SSamuel Thibault 
2662067fd92SSamuel Thibault 	while (--timeout > 0) {
2672067fd92SSamuel Thibault 		if ((dt_getstatus() & bit) == bit)
2682067fd92SSamuel Thibault 			return 1;
2692067fd92SSamuel Thibault 		udelay(50);
2702067fd92SSamuel Thibault 	}
2712067fd92SSamuel Thibault 	return 0;
2722067fd92SSamuel Thibault }
2732067fd92SSamuel Thibault 
dt_wait_dma(void)2742067fd92SSamuel Thibault static int dt_wait_dma(void)
2752067fd92SSamuel Thibault {
2762067fd92SSamuel Thibault 	int timeout = 100, state = dma_state;
2772067fd92SSamuel Thibault 
2782067fd92SSamuel Thibault 	if (!dt_waitbit(STAT_dma_ready))
2792067fd92SSamuel Thibault 		return 0;
2802067fd92SSamuel Thibault 	while (--timeout > 0) {
2812067fd92SSamuel Thibault 		if ((dt_getstatus() & STAT_dma_state) == state)
2822067fd92SSamuel Thibault 			return 1;
2832067fd92SSamuel Thibault 		udelay(50);
2842067fd92SSamuel Thibault 	}
2852067fd92SSamuel Thibault 	dma_state = dt_getstatus() & STAT_dma_state;
2862067fd92SSamuel Thibault 	return 1;
2872067fd92SSamuel Thibault }
2882067fd92SSamuel Thibault 
dt_ctrl(u_int cmd)2892067fd92SSamuel Thibault static int dt_ctrl(u_int cmd)
2902067fd92SSamuel Thibault {
2912067fd92SSamuel Thibault 	int timeout = 10;
2922067fd92SSamuel Thibault 
2932067fd92SSamuel Thibault 	if (!dt_waitbit(STAT_cmd_ready))
2942067fd92SSamuel Thibault 		return -1;
2952067fd92SSamuel Thibault 	outb_p(0, speakup_info.port_tts + 2);
2962067fd92SSamuel Thibault 	outb_p(0, speakup_info.port_tts + 3);
2972067fd92SSamuel Thibault 	dt_getstatus();
2982067fd92SSamuel Thibault 	dt_sendcmd(CMD_control | cmd);
2992067fd92SSamuel Thibault 	outb_p(0, speakup_info.port_tts + 6);
3002067fd92SSamuel Thibault 	while (dt_getstatus() & STAT_cmd_ready) {
3012067fd92SSamuel Thibault 		udelay(20);
3022067fd92SSamuel Thibault 		if (--timeout == 0)
3032067fd92SSamuel Thibault 			break;
3042067fd92SSamuel Thibault 	}
3052067fd92SSamuel Thibault 	dt_sendcmd(CMD_null);
3062067fd92SSamuel Thibault 	return 0;
3072067fd92SSamuel Thibault }
3082067fd92SSamuel Thibault 
synth_flush(struct spk_synth * synth)3092067fd92SSamuel Thibault static void synth_flush(struct spk_synth *synth)
3102067fd92SSamuel Thibault {
3112067fd92SSamuel Thibault 	int timeout = 10;
3122067fd92SSamuel Thibault 
3132067fd92SSamuel Thibault 	if (is_flushing)
3142067fd92SSamuel Thibault 		return;
3152067fd92SSamuel Thibault 	is_flushing = 4;
3162067fd92SSamuel Thibault 	in_escape = 0;
3172067fd92SSamuel Thibault 	while (dt_ctrl(CTRL_flush)) {
3182067fd92SSamuel Thibault 		if (--timeout == 0)
3192067fd92SSamuel Thibault 			break;
3202067fd92SSamuel Thibault 		udelay(50);
3212067fd92SSamuel Thibault 	}
3222067fd92SSamuel Thibault 	for (timeout = 0; timeout < 10; timeout++) {
3232067fd92SSamuel Thibault 		if (dt_waitbit(STAT_dma_ready))
3242067fd92SSamuel Thibault 			break;
3252067fd92SSamuel Thibault 		udelay(50);
3262067fd92SSamuel Thibault 	}
3272067fd92SSamuel Thibault 	outb_p(DMA_sync, speakup_info.port_tts + 4);
3282067fd92SSamuel Thibault 	outb_p(0, speakup_info.port_tts + 4);
3292067fd92SSamuel Thibault 	udelay(100);
3302067fd92SSamuel Thibault 	for (timeout = 0; timeout < 10; timeout++) {
3312067fd92SSamuel Thibault 		if (!(dt_getstatus() & STAT_flushing))
3322067fd92SSamuel Thibault 			break;
3332067fd92SSamuel Thibault 		udelay(50);
3342067fd92SSamuel Thibault 	}
3352067fd92SSamuel Thibault 	dma_state = dt_getstatus() & STAT_dma_state;
3362067fd92SSamuel Thibault 	dma_state ^= STAT_dma_state;
3372067fd92SSamuel Thibault 	is_flushing = 0;
3382067fd92SSamuel Thibault }
3392067fd92SSamuel Thibault 
dt_sendchar(char ch)3402067fd92SSamuel Thibault static int dt_sendchar(char ch)
3412067fd92SSamuel Thibault {
3422067fd92SSamuel Thibault 	if (!dt_wait_dma())
3432067fd92SSamuel Thibault 		return -1;
3442067fd92SSamuel Thibault 	if (!(dt_stat & STAT_rr_char))
3452067fd92SSamuel Thibault 		return -2;
3462067fd92SSamuel Thibault 	outb_p(DMA_single_in, speakup_info.port_tts + 4);
3472067fd92SSamuel Thibault 	outb_p(ch, speakup_info.port_tts + 4);
3482067fd92SSamuel Thibault 	dma_state ^= STAT_dma_state;
3492067fd92SSamuel Thibault 	return 0;
3502067fd92SSamuel Thibault }
3512067fd92SSamuel Thibault 
testkernel(void)3522067fd92SSamuel Thibault static int testkernel(void)
3532067fd92SSamuel Thibault {
3542067fd92SSamuel Thibault 	int status = 0;
3552067fd92SSamuel Thibault 
3562067fd92SSamuel Thibault 	if (dt_getstatus() == 0xffff) {
3572067fd92SSamuel Thibault 		status = -1;
3582067fd92SSamuel Thibault 		goto oops;
3592067fd92SSamuel Thibault 	}
3602067fd92SSamuel Thibault 	dt_sendcmd(CMD_sync);
3612067fd92SSamuel Thibault 	if (!dt_waitbit(STAT_cmd_ready))
3622067fd92SSamuel Thibault 		status = -2;
3632067fd92SSamuel Thibault 	else if (dt_stat & 0x8000)
3642067fd92SSamuel Thibault 		return 0;
3652067fd92SSamuel Thibault 	else if (dt_stat == 0x0dec)
3662067fd92SSamuel Thibault 		pr_warn("dec_pc at 0x%x, software not loaded\n",
3672067fd92SSamuel Thibault 			speakup_info.port_tts);
3682067fd92SSamuel Thibault 	status = -3;
3692067fd92SSamuel Thibault oops:	synth_release_region(speakup_info.port_tts, SYNTH_IO_EXTENT);
3702067fd92SSamuel Thibault 	speakup_info.port_tts = 0;
3712067fd92SSamuel Thibault 	return status;
3722067fd92SSamuel Thibault }
3732067fd92SSamuel Thibault 
do_catch_up(struct spk_synth * synth)3742067fd92SSamuel Thibault static void do_catch_up(struct spk_synth *synth)
3752067fd92SSamuel Thibault {
3762067fd92SSamuel Thibault 	u_char ch;
3772067fd92SSamuel Thibault 	static u_char last;
3782067fd92SSamuel Thibault 	unsigned long flags;
3792067fd92SSamuel Thibault 	unsigned long jiff_max;
3802067fd92SSamuel Thibault 	struct var_t *jiffy_delta;
3812067fd92SSamuel Thibault 	struct var_t *delay_time;
3822067fd92SSamuel Thibault 	int jiffy_delta_val;
3832067fd92SSamuel Thibault 	int delay_time_val;
3842067fd92SSamuel Thibault 
3852067fd92SSamuel Thibault 	jiffy_delta = spk_get_var(JIFFY);
3862067fd92SSamuel Thibault 	delay_time = spk_get_var(DELAY);
3872067fd92SSamuel Thibault 	spin_lock_irqsave(&speakup_info.spinlock, flags);
3882067fd92SSamuel Thibault 	jiffy_delta_val = jiffy_delta->u.n.value;
3892067fd92SSamuel Thibault 	spin_unlock_irqrestore(&speakup_info.spinlock, flags);
3902067fd92SSamuel Thibault 	jiff_max = jiffies + jiffy_delta_val;
3912067fd92SSamuel Thibault 
3922067fd92SSamuel Thibault 	while (!kthread_should_stop()) {
3932067fd92SSamuel Thibault 		spin_lock_irqsave(&speakup_info.spinlock, flags);
3942067fd92SSamuel Thibault 		if (speakup_info.flushing) {
3952067fd92SSamuel Thibault 			speakup_info.flushing = 0;
3962067fd92SSamuel Thibault 			spin_unlock_irqrestore(&speakup_info.spinlock, flags);
3972067fd92SSamuel Thibault 			synth->flush(synth);
3982067fd92SSamuel Thibault 			continue;
3992067fd92SSamuel Thibault 		}
4002067fd92SSamuel Thibault 		synth_buffer_skip_nonlatin1();
4012067fd92SSamuel Thibault 		if (synth_buffer_empty()) {
4022067fd92SSamuel Thibault 			spin_unlock_irqrestore(&speakup_info.spinlock, flags);
4032067fd92SSamuel Thibault 			break;
4042067fd92SSamuel Thibault 		}
4052067fd92SSamuel Thibault 		ch = synth_buffer_peek();
4062067fd92SSamuel Thibault 		set_current_state(TASK_INTERRUPTIBLE);
4072067fd92SSamuel Thibault 		delay_time_val = delay_time->u.n.value;
4082067fd92SSamuel Thibault 		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
4092067fd92SSamuel Thibault 		if (ch == '\n')
4102067fd92SSamuel Thibault 			ch = 0x0D;
4112067fd92SSamuel Thibault 		if (dt_sendchar(ch)) {
4122067fd92SSamuel Thibault 			schedule_timeout(msecs_to_jiffies(delay_time_val));
4132067fd92SSamuel Thibault 			continue;
4142067fd92SSamuel Thibault 		}
4152067fd92SSamuel Thibault 		set_current_state(TASK_RUNNING);
4162067fd92SSamuel Thibault 		spin_lock_irqsave(&speakup_info.spinlock, flags);
4172067fd92SSamuel Thibault 		synth_buffer_getc();
4182067fd92SSamuel Thibault 		spin_unlock_irqrestore(&speakup_info.spinlock, flags);
4192067fd92SSamuel Thibault 		if (ch == '[') {
4202067fd92SSamuel Thibault 			in_escape = 1;
4212067fd92SSamuel Thibault 		} else if (ch == ']') {
4222067fd92SSamuel Thibault 			in_escape = 0;
4232067fd92SSamuel Thibault 		} else if (ch <= SPACE) {
4242067fd92SSamuel Thibault 			if (!in_escape && strchr(",.!?;:", last))
4252067fd92SSamuel Thibault 				dt_sendchar(PROCSPEECH);
4262067fd92SSamuel Thibault 			if (time_after_eq(jiffies, jiff_max)) {
4272067fd92SSamuel Thibault 				if (!in_escape)
4282067fd92SSamuel Thibault 					dt_sendchar(PROCSPEECH);
4292067fd92SSamuel Thibault 				spin_lock_irqsave(&speakup_info.spinlock,
4302067fd92SSamuel Thibault 						  flags);
4312067fd92SSamuel Thibault 				jiffy_delta_val = jiffy_delta->u.n.value;
4322067fd92SSamuel Thibault 				delay_time_val = delay_time->u.n.value;
4332067fd92SSamuel Thibault 				spin_unlock_irqrestore(&speakup_info.spinlock,
4342067fd92SSamuel Thibault 						       flags);
4352067fd92SSamuel Thibault 				schedule_timeout(msecs_to_jiffies
4362067fd92SSamuel Thibault 						 (delay_time_val));
4372067fd92SSamuel Thibault 				jiff_max = jiffies + jiffy_delta_val;
4382067fd92SSamuel Thibault 			}
4392067fd92SSamuel Thibault 		}
4402067fd92SSamuel Thibault 		last = ch;
4412067fd92SSamuel Thibault 		ch = 0;
4422067fd92SSamuel Thibault 	}
4432067fd92SSamuel Thibault 	if (!in_escape)
4442067fd92SSamuel Thibault 		dt_sendchar(PROCSPEECH);
4452067fd92SSamuel Thibault }
4462067fd92SSamuel Thibault 
synth_immediate(struct spk_synth * synth,const char * buf)4472067fd92SSamuel Thibault static const char *synth_immediate(struct spk_synth *synth, const char *buf)
4482067fd92SSamuel Thibault {
4492067fd92SSamuel Thibault 	u_char ch;
4502067fd92SSamuel Thibault 
4512067fd92SSamuel Thibault 	while ((ch = *buf)) {
4522067fd92SSamuel Thibault 		if (ch == '\n')
4532067fd92SSamuel Thibault 			ch = PROCSPEECH;
4542067fd92SSamuel Thibault 		if (dt_sendchar(ch))
4552067fd92SSamuel Thibault 			return buf;
4562067fd92SSamuel Thibault 		buf++;
4572067fd92SSamuel Thibault 	}
4582067fd92SSamuel Thibault 	return NULL;
4592067fd92SSamuel Thibault }
4602067fd92SSamuel Thibault 
synth_probe(struct spk_synth * synth)4612067fd92SSamuel Thibault static int synth_probe(struct spk_synth *synth)
4622067fd92SSamuel Thibault {
4632067fd92SSamuel Thibault 	int i = 0, failed = 0;
4642067fd92SSamuel Thibault 
4652067fd92SSamuel Thibault 	pr_info("Probing for %s.\n", synth->long_name);
4662067fd92SSamuel Thibault 	for (i = 0; synth_portlist[i]; i++) {
4672067fd92SSamuel Thibault 		if (synth_request_region(synth_portlist[i], SYNTH_IO_EXTENT)) {
4682067fd92SSamuel Thibault 			pr_warn("request_region: failed with 0x%x, %d\n",
4692067fd92SSamuel Thibault 				synth_portlist[i], SYNTH_IO_EXTENT);
4702067fd92SSamuel Thibault 			continue;
4712067fd92SSamuel Thibault 		}
4722067fd92SSamuel Thibault 		speakup_info.port_tts = synth_portlist[i];
4732067fd92SSamuel Thibault 		failed = testkernel();
4742067fd92SSamuel Thibault 		if (failed == 0)
4752067fd92SSamuel Thibault 			break;
4762067fd92SSamuel Thibault 	}
4772067fd92SSamuel Thibault 	if (failed) {
4782067fd92SSamuel Thibault 		pr_info("%s: not found\n", synth->long_name);
4792067fd92SSamuel Thibault 		return -ENODEV;
4802067fd92SSamuel Thibault 	}
4812067fd92SSamuel Thibault 	pr_info("%s: %03x-%03x, Driver Version %s,\n", synth->long_name,
4822067fd92SSamuel Thibault 		speakup_info.port_tts, speakup_info.port_tts + 7,
4832067fd92SSamuel Thibault 		synth->version);
4842067fd92SSamuel Thibault 	synth->alive = 1;
4852067fd92SSamuel Thibault 	return 0;
4862067fd92SSamuel Thibault }
4872067fd92SSamuel Thibault 
dtpc_release(struct spk_synth * synth)4881941ab1dSSamuel Thibault static void dtpc_release(struct spk_synth *synth)
4892067fd92SSamuel Thibault {
4902067fd92SSamuel Thibault 	spk_stop_serial_interrupt();
4912067fd92SSamuel Thibault 	if (speakup_info.port_tts)
4922067fd92SSamuel Thibault 		synth_release_region(speakup_info.port_tts, SYNTH_IO_EXTENT);
4932067fd92SSamuel Thibault 	speakup_info.port_tts = 0;
4942067fd92SSamuel Thibault }
4952067fd92SSamuel Thibault 
4962067fd92SSamuel Thibault module_param_named(start, synth_dec_pc.startup, short, 0444);
497*b75cfeb1SOsama Muhammad module_param_named(rate, vars[RATE_ID].u.n.default_val, int, 0444);
498*b75cfeb1SOsama Muhammad module_param_named(pitch, vars[PITCH_ID].u.n.default_val, int, 0444);
499*b75cfeb1SOsama Muhammad module_param_named(inflection, vars[INFLECTION_ID].u.n.default_val, int, 0444);
500*b75cfeb1SOsama Muhammad module_param_named(vol, vars[VOL_ID].u.n.default_val, int, 0444);
501*b75cfeb1SOsama Muhammad module_param_named(punct, vars[PUNCT_ID].u.n.default_val, int, 0444);
502*b75cfeb1SOsama Muhammad module_param_named(voice, vars[VOICE_ID].u.n.default_val, int, 0444);
503*b75cfeb1SOsama Muhammad module_param_named(direct, vars[DIRECT_ID].u.n.default_val, int, 0444);
504*b75cfeb1SOsama Muhammad 
505*b75cfeb1SOsama Muhammad 
506*b75cfeb1SOsama Muhammad 
5072067fd92SSamuel Thibault 
5082067fd92SSamuel Thibault MODULE_PARM_DESC(start, "Start the synthesizer once it is loaded.");
509*b75cfeb1SOsama Muhammad MODULE_PARM_DESC(rate, "Set the rate variable on load.");
510*b75cfeb1SOsama Muhammad MODULE_PARM_DESC(pitch, "Set the pitch variable on load.");
511*b75cfeb1SOsama Muhammad MODULE_PARM_DESC(inflection, "Set the inflection variable on load.");
512*b75cfeb1SOsama Muhammad MODULE_PARM_DESC(vol, "Set the vol variable on load.");
513*b75cfeb1SOsama Muhammad MODULE_PARM_DESC(punct, "Set the punct variable on load.");
514*b75cfeb1SOsama Muhammad MODULE_PARM_DESC(voice, "Set the voice variable on load.");
515*b75cfeb1SOsama Muhammad MODULE_PARM_DESC(direct, "Set the direct variable on load.");
5162067fd92SSamuel Thibault 
5172067fd92SSamuel Thibault module_spk_synth(synth_dec_pc);
5182067fd92SSamuel Thibault 
5192067fd92SSamuel Thibault MODULE_AUTHOR("Kirk Reiser <kirk@braille.uwo.ca>");
5202067fd92SSamuel Thibault MODULE_AUTHOR("David Borowski");
5212067fd92SSamuel Thibault MODULE_DESCRIPTION("Speakup support for DECtalk PC synthesizers");
5222067fd92SSamuel Thibault MODULE_LICENSE("GPL");
5232067fd92SSamuel Thibault MODULE_VERSION(DRV_VERSION);
524