Searched refs:dtr1 (Results 1 – 2 of 2) sorted by relevance
68 u32 dtr0, dtr1, dtr2, dtr3, dtr4; in prog_ddr_timing_control() local77 dtr1 = msg_port_read(MEM_CTLR, DTR1); in prog_ddr_timing_control()108 dtr1 &= ~DTR1_TWCL_MASK; in prog_ddr_timing_control()110 dtr1 |= (wl - 3); in prog_ddr_timing_control()111 dtr1 &= ~DTR1_TWTP_MASK; in prog_ddr_timing_control()112 dtr1 |= ((wl + 4 + twr - 14) << 8); /* Change to tWTP */ in prog_ddr_timing_control()113 dtr1 &= ~DTR1_TRTP_MASK; in prog_ddr_timing_control()114 dtr1 |= ((MMAX(trtp, 4) - 3) << 28); /* 4 bit DRAM Clock */ in prog_ddr_timing_control()115 dtr1 &= ~DTR1_TRRD_MASK; in prog_ddr_timing_control()116 dtr1 |= ((trrd - 4) << 24); /* 4 bit DRAM Clock */ in prog_ddr_timing_control()[all …]
33 u32 dtr1; /* 0xa0 data training register 1 */ member