Searched refs:dtr0 (Results 1 – 2 of 2) sorted by relevance
68 u32 dtr0, dtr1, dtr2, dtr3, dtr4; in prog_ddr_timing_control() local76 dtr0 = msg_port_read(MEM_CTLR, DTR0); in prog_ddr_timing_control()98 dtr0 &= ~DTR0_DFREQ_MASK; in prog_ddr_timing_control()99 dtr0 |= mrc_params->ddr_speed; in prog_ddr_timing_control()100 dtr0 &= ~DTR0_TCL_MASK; in prog_ddr_timing_control()102 dtr0 |= ((tcl - 5) << 12); in prog_ddr_timing_control()103 dtr0 &= ~DTR0_TRP_MASK; in prog_ddr_timing_control()104 dtr0 |= ((trp - 5) << 4); /* 5 bit DRAM Clock */ in prog_ddr_timing_control()105 dtr0 &= ~DTR0_TRCD_MASK; in prog_ddr_timing_control()106 dtr0 |= ((trcd - 5) << 8); /* 5 bit DRAM Clock */ in prog_ddr_timing_control()[all …]
32 u32 dtr0; /* 0x9c data training register 0 */ member