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Searched refs:dtpr2 (Results 1 – 17 of 17) sorted by relevance

/openbmc/u-boot/board/ti/ks2_evm/
H A Dddr3_k2g.c29 .dtpr2 = 0x50022A00ul,
69 .dtpr2 = 0x50023600ul,
130 .dtpr2 = 0x50022A00ul,
H A Dddr3_cfg.c27 .dtpr2 = 0x5002D200ul,
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3_spd.c33 debug_ddr_cfg("dtpr2 0x%08X\n", ptr->dtpr2); in dump_phy_config()
335 spd_cb->phy_cfg.dtpr2 = 0 << 31 | 1 << 30 | 0 << 29 | in init_ddr3param()
338 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xp > spd->t_xpdll) ? in init_ddr3param()
342 spd_cb->phy_cfg.dtpr2 |= (((spd->t_xs > spd->t_xsdll) ? in init_ddr3param()
H A Dddr3.c51 __raw_writel(phy_cfg->dtpr2, base + KS2_DDRPHY_DTPR2_OFFSET); in ddr3_init_ddrphy()
/openbmc/u-boot/board/imgtec/ci20/
H A Dci20.c299 .dtpr2 = 0x10042a00,
343 .dtpr2 = 0x10042a00,
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dddr3.h27 unsigned int dtpr2; member
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h84 u32 dtpr2; member
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr.h136 u32 dtpr2; member
H A Dstm32mp1_ddr_regs.h156 u32 dtpr2; /* 0x3C DRAM Timing Parameters2*/ member
H A Dstm32mp1_ddr.c145 DDRPHY_REG_TIMING(dtpr2),
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dsdram.c85 writel(ddr_config->dtpr2, ddr_phy_regs + DDRP_DTPR2); in ddr_phy_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a23.h183 u32 dtpr2; /* 0x50 dram timing parameters register 2 */ member
H A Ddram_sun6i.h172 u32 dtpr2; /* 0x3c dram timing parameters register 2 */ member
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c136 writel(dram_para.tpr4, &mctl_phy->dtpr2); in mctl_init()
H A Ddram_sun6i.c144 (MCTL_TEXSR << 0), &mctl_phy->dtpr2); in mctl_channel_init()
/openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/
H A Djz4780_dram.h446 u32 dtpr2; /* DRAM Timing Parameters Register 2 */ member
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt91 dtpr2