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Searched refs:dtpr0 (Results 1 – 19 of 19) sorted by relevance

/openbmc/u-boot/board/ti/ks2_evm/
H A Dddr3_k2g.c27 .dtpr0 = 0x550F6644ul,
67 .dtpr0 = 0x6D147744ul,
128 .dtpr0 = 0x550E6644ul,
H A Dddr3_cfg.c25 .dtpr0 = 0x9D5CBB66ul,
/openbmc/u-boot/board/imgtec/ci20/
H A Dci20.c297 .dtpr0 = 0x2a8f6690,
341 .dtpr0 = 0x2c906690,
/openbmc/u-boot/arch/arm/mach-keystone/include/mach/
H A Dddr3.h25 unsigned int dtpr0; member
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram.h82 u32 dtpr0; member
/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr.h134 u32 dtpr0; member
H A Dstm32mp1_ddr_regs.h154 u32 dtpr0; /* 0x34 DRAM Timing Parameters0*/ member
H A Dstm32mp1_ddr.c143 DDRPHY_REG_TIMING(dtpr0),
/openbmc/u-boot/arch/arm/mach-keystone/
H A Dddr3_spd.c31 debug_ddr_cfg("dtpr0 0x%08X\n", ptr->dtpr0); in dump_phy_config()
325 spd_cb->phy_cfg.dtpr0 = (spd->t_rc & 0x3f) << 26 | in init_ddr3param()
H A Dddr3.c49 __raw_writel(phy_cfg->dtpr0, base + KS2_DDRPHY_DTPR0_OFFSET); in ddr3_init_ddrphy()
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dsdram.c83 writel(ddr_config->dtpr0, ddr_phy_regs + DDRP_DTPR0); in ddr_phy_init()
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddram_sun8i_a23.h181 u32 dtpr0; /* 0x48 dram timing parameters register 0 */ member
H A Ddram_sun6i.h170 u32 dtpr0; /* 0x34 dram timing parameters register 0 */ member
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun8i_a23.c135 writel(dram_para.tpr3, &mctl_phy->dtpr0); in mctl_init()
H A Ddram_sun6i.c136 &mctl_phy->dtpr0); in mctl_channel_init()
/openbmc/u-boot/arch/mips/mach-jz47xx/include/mach/
H A Djz4780_dram.h444 u32 dtpr0; /* DRAM Timing Parameters Register 0 */ member
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Drockchip,rk3288-dmc.txt89 dtpr0
/openbmc/u-boot/drivers/ram/rockchip/
H A Dsdram_rk3188.c266 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()
H A Dsdram_rk3288.c300 copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, in phy_cfg()