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Searched refs:dram_type (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/ast/
H A Dast_main.c340 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()
356 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()
360 ast->dram_type = AST_DRAM_2Gx16; in ast_get_dram_info()
363 ast->dram_type = AST_DRAM_4Gx16; in ast_get_dram_info()
366 ast->dram_type = AST_DRAM_8Gx16; in ast_get_dram_info()
372 ast->dram_type = AST_DRAM_512Mx16; in ast_get_dram_info()
376 ast->dram_type = AST_DRAM_1Gx16; in ast_get_dram_info()
379 ast->dram_type = AST_DRAM_2Gx16; in ast_get_dram_info()
382 ast->dram_type = AST_DRAM_4Gx16; in ast_get_dram_info()
389 ast->dram_type = AST_DRAM_512Mx16; in ast_get_dram_info()
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H A Dast_post.c285 if (ast->dram_type == AST_DRAM_1Gx16) in ast_init_dram_reg()
287 else if (ast->dram_type == AST_DRAM_1Gx32) in ast_init_dram_reg()
361 u32 dram_type; member
1585 param.dram_type = AST_DDR3; in ast_post_chip_2300()
1588 param.dram_type = AST_DDR2; in ast_post_chip_2300()
1623 if (param.dram_type == AST_DDR3) { in ast_post_chip_2300()
H A Dast_drv.h200 uint32_t dram_type; member
/openbmc/linux/arch/mips/ralink/
H A Dmt7620.c46 static int dram_type; variable
53 switch (dram_type) { in mt7620_dram_init()
79 switch (dram_type) { in mt7628_dram_init()
233 dram_type = cfg0 & DRAM_TYPE_MT7628_MASK; in prom_soc_init()
235 dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & in prom_soc_init()
237 if (dram_type == SYSCFG0_DRAM_TYPE_UNKNOWN) in prom_soc_init()
238 dram_type = SYSCFG0_DRAM_TYPE_SDRAM; in prom_soc_init()
/openbmc/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c619 u32 value, dram_type; in tegra210_emc_r21021_set_clock() local
631 dram_type = value >> EMC_FBIO_CFG5_DRAM_TYPE_SHIFT; in tegra210_emc_r21021_set_clock()
638 dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()
641 if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()
645 (dram_type == DRAM_TYPE_LPDDR2)) in tegra210_emc_r21021_set_clock()
677 emc_dbg(emc, INFO, "DRAM type = %d\n", dram_type); in tegra210_emc_r21021_set_clock()
863 if (src_clk_period > 50000 && dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()
874 if (dram_type == DRAM_TYPE_LPDDR4) in tegra210_emc_r21021_set_clock()
876 else if (dram_type == DRAM_TYPE_LPDDR2 || is_lpddr3) in tegra210_emc_r21021_set_clock()
879 else if (dram_type == DRAM_TYPE_DDR3) in tegra210_emc_r21021_set_clock()
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H A Dtegra124-emc.c490 enum emc_dram_type dram_type; member
629 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
724 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_prepare_timing_change()
751 if (emc->dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_OFF) in tegra_emc_prepare_timing_change()
757 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
766 if (emc->dram_type == DRAM_TYPE_DDR3) in tegra_emc_prepare_timing_change()
774 if (emc->dram_type == DRAM_TYPE_DDR3) { in tegra_emc_prepare_timing_change()
849 if (emc->dram_type == DRAM_TYPE_LPDDR3 && in tegra_emc_complete_timing_change()
857 if (emc->dram_type == DRAM_TYPE_DDR3 && in tegra_emc_complete_timing_change()
901 emc->dram_type = readl(emc->regs + EMC_FBIO_CFG5); in emc_init()
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H A Dtegra30-emc.c527 enum emc_dram_type dram_type; in emc_prepare_timing_change() local
572 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_prepare_timing_change()
648 if (dram_type == DRAM_TYPE_DDR3 && dll_change == DLL_CHANGE_ON) { in emc_prepare_timing_change()
701 if (dram_type == DRAM_TYPE_DDR3) { in emc_prepare_timing_change()
731 if (dram_type == DRAM_TYPE_DDR3) in emc_prepare_timing_change()
736 if (dram_type == DRAM_TYPE_DDR3) { in emc_prepare_timing_change()
1123 enum emc_dram_type dram_type; in emc_setup_hw() local
1128 dram_type = fbio_cfg5 & EMC_FBIO_CFG5_DRAM_TYPE_MASK; in emc_setup_hw()
1136 switch (dram_type) { in emc_setup_hw()
1162 switch (dram_type) { in emc_setup_hw()
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H A Dtegra20-emc.c601 enum emc_dram_type dram_type; in emc_setup_hw() local
641 dram_type = FIELD_GET(EMC_FBIO_CFG5_DRAM_TYPE, emc_fbio); in emc_setup_hw()
643 switch (dram_type) { in emc_setup_hw()
665 if (dram_type == DRAM_TYPE_LPDDR2) { in emc_setup_hw()
H A Dtegra210-emc-core.c772 if ((emc->dram_type != DRAM_TYPE_LPDDR2 && in tegra210_emc_set_refresh()
773 emc->dram_type != DRAM_TYPE_LPDDR4) || in tegra210_emc_set_refresh()
1774 emc->dram_type = value & 0x3; in tegra210_emc_detect()
H A Dtegra210-emc.h908 unsigned int dram_type; member
/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c96 u32 dram_type; member
459 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
572 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
592 writel(MCTL_MSTR_DEVICETYPE(para->dram_type) | in mctl_channel_init()
593 MCTL_MSTR_BURSTLENGTH(para->dram_type) | in mctl_channel_init()
598 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
629 if (para->dram_type != DRAM_TYPE_DDR3) in mctl_channel_init()
663 if (para->dram_type == DRAM_TYPE_DDR3) { in mctl_channel_init()
717 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
749 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
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H A Ddram_sun8i_a83t.c27 u8 dram_type; member
37 MCTL_CR_CHANNEL(1) | MCTL_CR_DRAM_TYPE(para->dram_type) | in mctl_set_cr()
133 if (para->dram_type == DRAM_TYPE_DDR3) { in auto_set_timing_para()
138 } else if (para->dram_type == DRAM_TYPE_LPDDR3) { in auto_set_timing_para()
323 if (para->dram_type == DRAM_TYPE_LPDDR3) in mctl_channel_init()
337 if (para->dram_type == DRAM_TYPE_DDR3) in mctl_channel_init()
443 para.dram_type = CONFIG_DRAM_TYPE; in sunxi_dram_init()
/openbmc/linux/drivers/edac/
H A Damd64_edac.c1430 if (pvt->dram_type == MEM_LRDDR3) { in debug_dump_dramcfg_low()
1638 if (umc->dram_type == MEM_LRDDR4 || umc->dram_type == MEM_LRDDR5) { in umc_dump_misc_regs()
1820 umc->dram_type = MEM_EMPTY; in umc_determine_memory_type()
1830 umc->dram_type = MEM_LRDDR5; in umc_determine_memory_type()
1832 umc->dram_type = MEM_RDDR5; in umc_determine_memory_type()
1834 umc->dram_type = MEM_DDR5; in umc_determine_memory_type()
1837 umc->dram_type = MEM_LRDDR4; in umc_determine_memory_type()
1839 umc->dram_type = MEM_RDDR4; in umc_determine_memory_type()
1841 umc->dram_type = MEM_DDR4; in umc_determine_memory_type()
1844 edac_dbg(1, " UMC%d DIMM type: %s\n", i, edac_mem_types[umc->dram_type]); in umc_determine_memory_type()
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H A Daspeed_edac.c234 u32 nr_pages, dram_type; in init_csrows() local
265 dram_type = (reg04 & ASPEED_MCR_CONF_DRAM_TYPE) ? MEM_DDR4 : MEM_DDR3; in init_csrows()
268 dimm->mtype = dram_type; in init_csrows()
H A Damd64_edac.h315 enum mem_type dram_type; member
384 enum mem_type dram_type; member
/openbmc/u-boot/arch/x86/include/asm/arch-baytrail/fsp/
H A Dfsp_vpd.h13 uint8_t dram_type; member
/openbmc/u-boot/arch/x86/cpu/baytrail/
H A Dfsp_configs.c134 mem->dram_type = fdtdec_get_int(blob, node, in update_fsp_configs()