Home
last modified time | relevance | path

Searched refs:dpll_hw_state (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c802 crtc_state->dpll_hw_state.fp0 = fp; in i9xx_update_pll_dividers()
803 crtc_state->dpll_hw_state.fp1 = fp2; in i9xx_update_pll_dividers()
876 crtc_state->dpll_hw_state.dpll = dpll; in i9xx_compute_dpll()
881 crtc_state->dpll_hw_state.dpll_md = dpll_md; in i9xx_compute_dpll()
933 crtc_state->dpll_hw_state.dpll = dpll; in i8xx_compute_dpll()
1059 crtc_state->dpll_hw_state.fp0 = fp; in ilk_update_pll_dividers()
1060 crtc_state->dpll_hw_state.fp1 = fp2; in ilk_update_pll_dividers()
1137 crtc_state->dpll_hw_state.dpll = dpll; in ilk_compute_dpll()
1212 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | in vlv_compute_dpll()
1215 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; in vlv_compute_dpll()
[all …]
H A Dintel_dpll_mgr.c575 &crtc_state->dpll_hw_state, in ibx_get_dpll()
585 pll, &crtc_state->dpll_hw_state); in ibx_get_dpll()
972 crtc_state->dpll_hw_state.wrpll = in hsw_ddi_wrpll_compute_dpll()
978 &crtc_state->dpll_hw_state); in hsw_ddi_wrpll_compute_dpll()
991 &crtc_state->dpll_hw_state, in hsw_ddi_wrpll_get_dpll()
1079 crtc_state->dpll_hw_state.spll = in hsw_ddi_spll_compute_dpll()
1092 return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state, in hsw_ddi_spll_get_dpll()
1156 pll, &crtc_state->dpll_hw_state); in hsw_get_dpll()
1731 crtc_state->dpll_hw_state.ctrl1 = ctrl1; in skl_ddi_hdmi_pll_dividers()
1732 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; in skl_ddi_hdmi_pll_dividers()
[all …]
H A Dintel_display.c1190 new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state; in intel_encoders_update_prepare()
2801 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in vlv_crtc_clock_get()
2829 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) in chv_crtc_clock_get()
2969 pipe_config->dpll_hw_state.dpll_md = tmp; in i9xx_get_pipe_config()
2982 pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv, in i9xx_get_pipe_config()
2985 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
2987 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv, in i9xx_get_pipe_config()
2991 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | in i9xx_get_pipe_config()
3822 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_pll_refclk()
3840 u32 dpll = pipe_config->dpll_hw_state.dpll; in i9xx_crtc_clock_get()
[all …]
H A Dintel_pch_display.c528 &crtc_state->dpll_hw_state); in ilk_pch_get_config()
531 tmp = crtc_state->dpll_hw_state.dpll; in ilk_pch_get_config()
H A Dintel_crtc_state_dump.c350 intel_dpll_dump_hw_state(i915, &pipe_config->dpll_hw_state); in intel_crtc_state_dump()
H A Dintel_display_types.h1175 struct intel_dpll_hw_state dpll_hw_state; member
H A Dintel_ddi.c3870 &crtc_state->dpll_hw_state);
3992 &crtc_state->dpll_hw_state); in hsw_ddi_get_config()