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Searched refs:dpll (Results 1 – 25 of 91) sorted by relevance

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/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll.c313 int pnv_calc_dpll_params(int refclk, struct dpll *clock) in pnv_calc_dpll_params()
325 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) in i9xx_dpll_compute_m() argument
327 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); in i9xx_dpll_compute_m()
330 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) in i9xx_calc_dpll_params()
342 int vlv_calc_dpll_params(int refclk, struct dpll *clock) in vlv_calc_dpll_params()
354 int chv_calc_dpll_params(int refclk, struct dpll *clock) in chv_calc_dpll_params()
373 const struct dpll *clock) in intel_pll_is_valid()
444 const struct dpll *match_clock, in i9xx_find_best_dpll()
445 struct dpll *best_clock) in i9xx_find_best_dpll()
448 struct dpll clock; in i9xx_find_best_dpll()
[all …]
H A Dintel_dpll.h11 struct dpll;
23 int vlv_calc_dpll_params(int refclk, struct dpll *clock);
24 int pnv_calc_dpll_params(int refclk, struct dpll *clock);
25 int i9xx_calc_dpll_params(int refclk, struct dpll *clock);
26 u32 i9xx_dpll_compute_fp(const struct dpll *dpll);
31 const struct dpll *dpll);
41 struct dpll *best_clock);
42 int chv_calc_dpll_params(int refclk, struct dpll *pll_clock);
H A Dintel_dpll_mgr.c121 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_atomic_duplicate_dpll_state()
122 struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_atomic_duplicate_dpll_state()
157 return &dev_priv->display.dpll.shared_dplls[id]; in intel_get_shared_dpll_by_id()
232 mutex_lock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
258 mutex_unlock(&dev_priv->display.dpll.lock); in intel_enable_shared_dpll()
281 mutex_lock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
304 mutex_unlock(&dev_priv->display.dpll.lock); in intel_disable_shared_dpll()
323 pll = &dev_priv->display.dpll.shared_dplls[i]; in intel_find_shared_dpll()
467 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in intel_shared_dpll_swap_state()
469 &dev_priv->display.dpll.shared_dplls[i]; in intel_shared_dpll_swap_state()
[all …]
H A Dintel_pch_refclk.c464 dev_priv->display.dpll.pch_ssc_use = 0; in lpt_init_pch_refclk()
468 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_SPLL); in lpt_init_pch_refclk()
473 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL1); in lpt_init_pch_refclk()
478 dev_priv->display.dpll.pch_ssc_use |= BIT(DPLL_ID_WRPLL2); in lpt_init_pch_refclk()
481 if (dev_priv->display.dpll.pch_ssc_use) in lpt_init_pch_refclk()
530 for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) { in ilk_init_pch_refclk()
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c107 u32 dpll = 0, fp = 0, dspcntr, pipeconf; in psb_intel_crtc_mode_set() local
158 dpll = DPLL_VGA_MODE_DIS; in psb_intel_crtc_mode_set()
160 dpll |= DPLLB_MODE_LVDS; in psb_intel_crtc_mode_set()
161 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
163 dpll |= DPLLB_MODE_DAC_SERIAL; in psb_intel_crtc_mode_set()
167 dpll |= DPLL_DVO_HIGH_SPEED; in psb_intel_crtc_mode_set()
168 dpll |= in psb_intel_crtc_mode_set()
173 dpll |= (1 << (clock.p1 - 1)) << 16; in psb_intel_crtc_mode_set()
176 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; in psb_intel_crtc_mode_set()
179 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; in psb_intel_crtc_mode_set()
[all …]
H A Doaktrail_crtc.c245 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
247 REG_WRITE_WITH_AUX(map->dpll, temp, i); in oaktrail_crtc_dpms()
248 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
251 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
253 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
256 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
258 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
317 temp = REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
319 REG_WRITE_WITH_AUX(map->dpll, in oaktrail_crtc_dpms()
321 REG_READ_WITH_AUX(map->dpll, i); in oaktrail_crtc_dpms()
[all …]
H A Dcdv_intel_display.c584 u32 dpll = 0, dspcntr, pipeconf; in cdv_intel_crtc_mode_set() local
665 dpll = DPLL_VGA_MODE_DIS; in cdv_intel_crtc_mode_set()
676 dpll |= DPLL_SYNCLOCK_ENABLE; in cdv_intel_crtc_mode_set()
722 REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE); in cdv_intel_crtc_mode_set()
723 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
758 dpll |= DPLL_VCO_ENABLE; in cdv_intel_crtc_mode_set()
767 REG_WRITE(map->dpll, in cdv_intel_crtc_mode_set()
768 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE); in cdv_intel_crtc_mode_set()
769 REG_READ(map->dpll); in cdv_intel_crtc_mode_set()
773 if (!(REG_READ(map->dpll) & DPLL_LOCK)) { in cdv_intel_crtc_mode_set()
[all …]
H A Dgma_display.c223 temp = REG_READ(map->dpll); in gma_crtc_dpms()
225 REG_WRITE(map->dpll, temp); in gma_crtc_dpms()
226 REG_READ(map->dpll); in gma_crtc_dpms()
229 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
230 REG_READ(map->dpll); in gma_crtc_dpms()
233 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in gma_crtc_dpms()
234 REG_READ(map->dpll); in gma_crtc_dpms()
311 temp = REG_READ(map->dpll); in gma_crtc_dpms()
313 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE); in gma_crtc_dpms()
314 REG_READ(map->dpll); in gma_crtc_dpms()
[all …]
H A Doaktrail_hdmi.c285 u32 dspcntr, pipeconf, dpll, temp; in oaktrail_crtc_hdmi_mode_set() local
295 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
296 if ((dpll & DPLL_PWRDN) == 0) { in oaktrail_crtc_hdmi_mode_set()
297 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); in oaktrail_crtc_hdmi_mode_set()
311 dpll = REG_READ(DPLL_CTRL); in oaktrail_crtc_hdmi_mode_set()
312 dpll &= ~DPLL_PDIV_MASK; in oaktrail_crtc_hdmi_mode_set()
313 dpll &= ~(DPLL_PWRDN | DPLL_RESET); in oaktrail_crtc_hdmi_mode_set()
317 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); in oaktrail_crtc_hdmi_mode_set()
/openbmc/linux/Documentation/devicetree/bindings/clock/ti/
H A Ddpll.txt18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
25 "ti,omap4-dpll-m4xen-clock",
26 "ti,omap4-dpll-j-type-clock",
27 "ti,omap5-mpu-dpll-clock",
[all …]
/openbmc/u-boot/arch/arm/mach-uniphier/clk/
H A DMakefile5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
14 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-ld4.o pll-ld4.o dpll-tail.o
15 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
16 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-ld4.o pll-ld4.o dpll-tail.o
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7xx-clocks.dtsi229 compatible = "ti,omap4-dpll-m4xen-clock";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
237 compatible = "ti,omap4-dpll-x2-clock";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
288 dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
299 compatible = "ti,omap4-dpll-core-clock";
305 dpll_core_x2_ck: clock-dpll-core-x2 {
307 compatible = "ti,omap4-dpll-x2-clock";
[all …]
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
H A Dam33xx-clocks.dtsi190 compatible = "ti,am3-dpll-core-clock";
196 dpll_core_x2_ck: clock-dpll-core-x2 {
198 compatible = "ti,am3-dpll-x2-clock";
203 dpll_core_m4_ck: clock-dpll-core-m4@480 {
213 dpll_core_m5_ck: clock-dpll-core-m5@484 {
223 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
235 compatible = "ti,am3-dpll-clock";
241 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
253 compatible = "ti,am3-dpll-no-gate-clock";
259 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]
/openbmc/linux/arch/arm/mach-omap1/
H A Dsram.S36 strh r0, [r2] @ set dpll into bypass mode
41 strh r0, [r2] @ write new dpll value
49 lock: ldrh r4, [r2], #0 @ read back dpll value
52 tst r4, #1 << 0 @ dpll rate locked?
/openbmc/u-boot/board/gumstix/pepper/
H A Dboard.c144 const struct dpll_params *dpll = get_dpll_ddr_params(); in sdram_init() local
152 if (dpll->m == 266) { in sdram_init()
153 config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data, in sdram_init()
156 else if (dpll->m == 400) { in sdram_init()
157 config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data, in sdram_init()
/openbmc/u-boot/arch/arm/lib/
H A Dasm-offsets.c191 DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl)); in main()
192 DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config)); in main()
193 DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op)); in main()
194 DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd)); in main()
195 DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn)); in main()
196 DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op)); in main()
197 DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd)); in main()
198 DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn)); in main()
/openbmc/linux/drivers/ata/
H A Dpata_hpt3x2n.c312 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_defer() local
319 if ((flags & USE_DPLL) != dpll && alt->qc_active) in hpt3x2n_qc_defer()
328 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); in hpt3x2n_qc_issue() local
330 if ((flags & USE_DPLL) != dpll) { in hpt3x2n_qc_issue()
332 flags |= dpll; in hpt3x2n_qc_issue()
335 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); in hpt3x2n_qc_issue()
H A Dpata_hpt37x.c948 int dpll, adjust; in hpt37x_init_one() local
951 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2; in hpt37x_init_one()
953 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
981 if (dpll == 3) in hpt37x_init_one()
987 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/
H A Drcar_du_crtc.c83 struct dpll_info *dpll, in rcar_du_dpll_divider() argument
147 dpll->n = n; in rcar_du_dpll_divider()
148 dpll->m = m; in rcar_du_dpll_divider()
149 dpll->fdpll = fdpll; in rcar_du_dpll_divider()
150 dpll->output = output; in rcar_du_dpll_divider()
162 dpll->output, dpll->fdpll, dpll->n, dpll->m, best_diff); in rcar_du_dpll_divider()
217 struct dpll_info dpll = { 0 }; in rcar_du_crtc_set_display_timing() local
227 rcar_du_dpll_divider(rcrtc, &dpll, extclk, target); in rcar_du_crtc_set_display_timing()
230 | DPLLCR_FDPLL(dpll.fdpll) in rcar_du_crtc_set_display_timing()
231 | DPLLCR_N(dpll.n) | DPLLCR_M(dpll.m) in rcar_du_crtc_set_display_timing()
/openbmc/linux/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, in intelfbhw_get_p1p2() argument
688 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; in intelfbhw_get_p1p2()
695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
697 if (dpll & DPLL_P1_FORCE_DIV2) in intelfbhw_get_p1p2()
700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; in intelfbhw_get_p1p2()
701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; in intelfbhw_get_p1p2()
1043 u32 *dpll, *fp0, *fp1; in intelfbhw_mode_to_hw() local
1058 dpll = &hw->dpll_b; in intelfbhw_mode_to_hw()
1070 dpll = &hw->dpll_a; in intelfbhw_mode_to_hw()
[all …]
/openbmc/u-boot/drivers/clk/
H A Dclk_zynqmp.c114 apll, dpll, vpll, enumerator
188 case dpll: in zynqmp_clk_get_register()
253 return dpll; in zynqmp_clk_get_cpu_pll()
272 return dpll; in zynqmp_clk_get_ddr_pll()
285 return dpll; in zynqmp_clk_get_peripheral_pll()
301 return dpll; in zynqmp_clk_get_wdt_pll()
/openbmc/u-boot/arch/arm/dts/
H A Dam43xx-clocks.dtsi200 compatible = "ti,am3-dpll-core-clock";
207 compatible = "ti,am3-dpll-x2-clock";
246 compatible = "ti,am3-dpll-clock";
264 compatible = "ti,am3-dpll-clock";
282 compatible = "ti,am3-dpll-clock";
301 compatible = "ti,am3-dpll-j-type-clock";
584 compatible = "ti,am3-dpll-clock";
661 compatible = "ti,am3-dpll-x2-clock";
H A Dam33xx-clocks.dtsi168 compatible = "ti,am3-dpll-core-clock";
175 compatible = "ti,am3-dpll-x2-clock";
208 compatible = "ti,am3-dpll-clock";
224 compatible = "ti,am3-dpll-no-gate-clock";
248 compatible = "ti,am3-dpll-no-gate-clock";
265 compatible = "ti,am3-dpll-no-gate-j-type-clock";
/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dsharkl3.dtsi123 dpll: dpll { label
124 compatible = "sprd,sc9863a-dpll";

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