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Searched refs:divr (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c302 c->divr = best_r - 1; in wrpll_configure_for_rate()
347 n = div_u64(n, c->divr + 1); in wrpll_calc_output_rate()
/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c332 c->divr = best_r - 1; in analogbits_wrpll_configure_for_rate()
369 n = div_u64(n, (c->divr + 1)); in analogbits_wrpll_calc_output_rate()
H A Danalogbits-wrpll-cln28hpc.h77 u8 divr; member
H A Dfu540-prci.c266 c->divr = v; in __prci_wrpll_unpack()
308 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; in __prci_wrpll_pack()
/openbmc/linux/include/linux/clk/
H A Danalogbits-wrpll-cln28hpc.h59 u8 divr; member
/openbmc/linux/drivers/media/dvb-frontends/
H A Dsi2165.c204 u8 divr = 1; /* 1..7 */ in si2165_init_pll() local
220 divr = 2; in si2165_init_pll()
227 divr = 2; in si2165_init_pll()
233 if (1624000000u * divr > ref_freq_hz * 2u * 63u) in si2165_init_pll()
237 divn = 1624000000u * divr / (ref_freq_hz * 2u * divp); in si2165_init_pll()
242 state->fvco_hz = ref_freq_hz / divr in si2165_init_pll()
251 buf[3] = divr; in si2165_init_pll()
/openbmc/u-boot/drivers/clk/
H A Dclk_stm32h7.c324 u8 divr; member
337 .divr = 2,
397 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; in configure_clocks()
/openbmc/linux/drivers/clk/sifive/
H A Dsifive-prci.c63 c->divr = v; in __prci_wrpll_unpack()
103 r |= c->divr << PRCI_COREPLLCFG0_DIVR_SHIFT; in __prci_wrpll_pack()