| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | clock.c | 89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll() argument
102 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask; in clock_ll_read_pll()
113 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll() argument
147 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift); in clock_start_pll()
535 u32 base, divm; in clock_get_rate() local
552 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask; in clock_get_rate()
566 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask; in clock_get_rate()
567 do_div(rate, divm); in clock_get_rate()
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| H A D | cpu.c | 170 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate() argument
187 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift); in pllx_set_rate()
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| /openbmc/u-boot/arch/arm/include/asm/arch-tegra/ |
| H A D | clock.h | 61 unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
88 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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| H A D | warmboot.h | 71 u32 divm:5; member
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra20/ |
| H A D | warmboot.c | 153 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
155 if (clock_ll_read_pll(CLOCK_ID_MEMORY, &divm, &divn, &divp, in warmboot_save_sdram_params()
158 scratch2.pllm_base_divm = divm; in warmboot_save_sdram_params()
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| /openbmc/u-boot/arch/arm/mach-tegra/tegra124/ |
| H A D | clock.c | 1066 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local
1086 for (divm = 1; divm < max_m && best_diff; divm++) { in clock_set_display_rate()
1087 cf = ref / divm; in clock_set_display_rate()
1107 best_m = divm; in clock_set_display_rate()
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| /openbmc/u-boot/drivers/clk/ |
| H A D | clk_stm32h7.c | 320 u8 divm; member
333 .divm = 4,
394 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; in configure_clocks()
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| H A D | clk_stm32mp1.c | 863 int divm, divn; in pll_get_fvco() local
870 divm = (cfgr1 & (RCC_PLLNCFGR1_DIVM_MASK)) >> RCC_PLLNCFGR1_DIVM_SHIFT; in pll_get_fvco()
874 pll_id, cfgr1, fracr, divn, divm); in pll_get_fvco()
888 ((unsigned long long)(divm + 1)) << 13); in pll_get_fvco()
890 fvco = (ulong)(refclk * (divn + 1) / (divm + 1)); in pll_get_fvco()
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| /openbmc/linux/drivers/clk/ |
| H A D | clk-stm32h7.c | 626 u8 divm; member
641 .divm = 4,
649 .divm = 12,
657 .divm = 20,
817 div->mshift = cfg->divm; in clk_register_stm32_pll()
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| H A D | clk-stm32mp1.c | 842 u32 frac, divm, divn; in pll_recalc_rate() local
847 divm = ((reg >> DIVM_SHIFT) & DIVM_MASK) + 1; in pll_recalc_rate()
851 do_div(rate, divm); in pll_recalc_rate()
856 do_div(rate_frac, (divm * 8192)); in pll_recalc_rate()
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| /openbmc/linux/drivers/media/dvb-frontends/ |
| H A D | si2165.c | 207 u8 divm = 8; in si2165_init_pll() local
244 state->adc_clk = state->fvco_hz / (divm * 4u); in si2165_init_pll()
249 buf[1] = divm; in si2165_init_pll()
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| /openbmc/linux/drivers/clk/tegra/ |
| H A D | clk-pll.c | 1021 u32 divn = 0, divm = 0, divp = 0; in clk_plle_recalc_rate() local
1026 divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll)); in clk_plle_recalc_rate()
1027 divm *= divp; in clk_plle_recalc_rate()
1030 do_div(rate, divm); in clk_plle_recalc_rate()
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