/openbmc/u-boot/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training.c | 92 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num); 93 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, 95 static int ddr3_tip_ddr3_auto_tune(u32 dev_num); 98 static int odt_test(u32 dev_num, enum hws_algo_type algo_type); 101 int adll_calibration(u32 dev_num, enum hws_access_type access_type, 103 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, 228 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id); 233 int ddr3_tip_tune_training_params(u32 dev_num, in ddr3_tip_tune_training_params() argument 279 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) in ddr3_tip_configure_cs() argument 289 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_configure_cs() [all …]
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H A D | ddr3_training_ip_flow.h | 61 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, 64 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id, 67 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, 69 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, 72 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, 74 int ddr3_tip_bus_read_modify_write(u32 dev_num, 79 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access, 82 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access, 86 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id, 88 int ddr3_tip_adjust_dqs(u32 dev_num); [all …]
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H A D | ddr3_training_ip_prv_if.h | 23 typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable); 25 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 28 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 31 u8 dev_num, enum mv_ddr_freq freq, 34 u8 dev_num, struct ddr3_device_info *info_ptr); 36 u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info); 38 u8 dev_num, u32 if_id, enum mv_ddr_freq freq); 39 typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum mv_ddr_freq *freq); 41 u32 dev_num, enum hws_access_type access_type, u32 dunit_id, 44 u32 dev_num, enum hws_access_type access_type, u32 dunit_id, [all …]
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H A D | ddr3_training_leveling.c | 22 static int ddr3_tip_dynamic_write_leveling_seq(u32 dev_num); 23 static int ddr3_tip_dynamic_read_leveling_seq(u32 dev_num); 24 static int ddr3_tip_dynamic_per_bit_read_leveling_seq(u32 dev_num); 25 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id, 27 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id, 37 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq) in ddr3_tip_dynamic_read_leveling() argument 50 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_dynamic_read_leveling() 65 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_read_leveling() 70 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_dynamic_read_leveling() 74 ddr3_tip_reset_fifo_ptr(dev_num); in ddr3_tip_dynamic_read_leveling() [all …]
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H A D | ddr3_debug.c | 111 int ddr3_tip_reg_dump(u32 dev_num) in ddr3_tip_reg_dump() argument 115 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_reg_dump() 124 (dev_num, ACCESS_TYPE_UNICAST, in ddr3_tip_reg_dump() 142 (dev_num, if_id, in ddr3_tip_reg_dump() 153 (dev_num, if_id, in ddr3_tip_reg_dump() 169 int ddr3_tip_init_config_func(u32 dev_num, in ddr3_tip_init_config_func() argument 175 memcpy(&config_func_info[dev_num], config_func, in ddr3_tip_init_config_func() 192 int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr) in ddr3_tip_get_device_info() argument 194 if (config_func_info[dev_num].tip_get_device_info_func != NULL) { in ddr3_tip_get_device_info() 195 return config_func_info[dev_num]. in ddr3_tip_get_device_info() [all …]
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H A D | ddr3_training_ip_engine.c | 314 u32 *ddr3_tip_get_buf_ptr(u32 dev_num, enum hws_search_dir search, in ddr3_tip_get_buf_ptr() argument 336 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, in ddr3_tip_ip_training() argument 357 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_ip_training() 379 (dev_num, access_type, interface_num, in ddr3_tip_ip_training() 383 (dev_num, access_type, interface_num, in ddr3_tip_ip_training() 388 (dev_num, access_type, interface_num, in ddr3_tip_ip_training() 392 (dev_num, access_type, interface_num, in ddr3_tip_ip_training() 398 ddr3_tip_load_pattern_to_odpg(dev_num, access_type, interface_num, in ddr3_tip_ip_training() 406 (dev_num, access_type, interface_num, direction, in ddr3_tip_ip_training() 414 (dev_num, access_type, interface_num, in ddr3_tip_ip_training() [all …]
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H A D | ddr3_training_pbs.c | 36 int ddr3_tip_pbs(u32 dev_num, enum pbs_dir pbs_mode) in ddr3_tip_pbs() argument 54 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_pbs() 63 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs() 68 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs() 75 ddr3_tip_read_adll_value(dev_num, nominal_adll, reg_addr, MASK_ALL_BITS); in ddr3_tip_pbs() 78 ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_pbs() 103 (dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_pbs() 190 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs() 197 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_pbs() 206 ddr3_tip_ip_training(dev_num, ACCESS_TYPE_MULTICAST, in ddr3_tip_pbs() [all …]
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H A D | ddr3_training_centralization.c | 27 static int ddr3_tip_centralization(u32 dev_num, u32 mode); 32 int ddr3_tip_centralization_rx(u32 dev_num) in ddr3_tip_centralization_rx() argument 34 CHECK_STATUS(ddr3_tip_special_rx(dev_num)); in ddr3_tip_centralization_rx() 35 CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_RX)); in ddr3_tip_centralization_rx() 43 int ddr3_tip_centralization_tx(u32 dev_num) in ddr3_tip_centralization_tx() argument 45 CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_TX)); in ddr3_tip_centralization_tx() 53 static int ddr3_tip_centralization(u32 dev_num, u32 mode) in ddr3_tip_centralization() argument 64 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_centralization() 84 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_centralization() 88 (dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_centralization() [all …]
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H A D | ddr3_training_hw_algo.c | 43 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) in ddr3_tip_write_additional_odt_setting() argument 52 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); in ddr3_tip_write_additional_odt_setting() 55 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting() 58 CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting() 77 (dev_num, if_id, in ddr3_tip_write_additional_odt_setting() 101 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting() 105 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, in ddr3_tip_write_additional_odt_setting() 113 int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4]) in get_valid_win_rx() argument 126 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, in get_valid_win_rx() 147 int ddr3_tip_vref(u32 dev_num) in ddr3_tip_vref() argument [all …]
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H A D | ddr3_training_ip_bist.h | 35 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, 37 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, 44 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, 46 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction, 48 int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num, 50 int ddr3_tip_print_regs(u32 dev_num); 51 int ddr3_tip_reg_dump(u32 dev_num); 52 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
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H A D | ddr3_init.h | 143 int ddr3_tip_enable_init_sequence(u32 dev_num); 152 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data); 153 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask); 156 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]); 157 int print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]); 158 int read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 160 int write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], 162 int ddr3_tip_restore_dunit_regs(u32 dev_num); 170 int ddr3_tip_tune_training_params(u32 dev_num, 179 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode); [all …]
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H A D | mv_ddr_plat.c | 184 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id, 190 static u32 ddr3_ctrl_get_junc_temp(u8 dev_num) in ddr3_ctrl_get_junc_temp() argument 224 static int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum mv_ddr_freq freq, in ddr3_tip_a38x_get_freq_config() argument 364 static int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable) in ddr3_tip_a38x_select_ddr_controller() argument 388 static int mv_ddr_sar_freq_get(int dev_num, enum mv_ddr_freq *freq) in mv_ddr_sar_freq_get() argument 482 static int ddr3_tip_a38x_get_medium_freq(int dev_num, enum mv_ddr_freq *freq) in ddr3_tip_a38x_get_medium_freq() argument 559 static int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr) in ddr3_tip_a38x_get_device_info() argument 639 static int mv_ddr_sw_db_init(u32 dev_num, u32 board_id) in mv_ddr_sw_db_init() argument 659 ddr3_tip_init_config_func(dev_num, &config_func); in mv_ddr_sw_db_init() 661 ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin); in mv_ddr_sw_db_init() [all …]
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H A D | ddr3_training_ip_centralization.h | 9 int ddr3_tip_centralization_tx(u32 dev_num); 10 int ddr3_tip_centralization_rx(u32 dev_num); 11 int ddr3_tip_print_centralization_result(u32 dev_num); 12 int ddr3_tip_special_rx(u32 dev_num);
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H A D | ddr3_training_ip_engine.h | 33 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type, 40 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern); 41 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num); 42 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id, 52 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, 63 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
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H A D | ddr3_training_ip.h | 136 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table); 137 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable); 138 int hws_ddr3_tip_init_controller(u32 dev_num, 140 int hws_ddr3_tip_load_topology_map(u32 dev_num, 142 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
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H A D | ddr3_training_hw_algo.h | 9 int ddr3_tip_vref(u32 dev_num); 10 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id); 11 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
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H A D | ddr3_training_ip_pbs.h | 36 int ddr3_tip_pbs_rx(u32 dev_num); 37 int ddr3_tip_print_all_pbs_result(u32 dev_num); 38 int ddr3_tip_pbs_tx(u32 dev_num);
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H A D | ddr3_training_bist.c | 12 static int ddr3_tip_bist_operation(u32 dev_num, 20 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, in ddr3_tip_bist_activate() argument 74 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, in ddr3_tip_bist_read_result() argument 86 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result() 92 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result() 99 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result() 105 ret = ddr3_tip_if_read(dev_num, ACCESS_TYPE_UNICAST, if_id, in ddr3_tip_bist_read_result() 118 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, in hws_ddr3_run_bist() argument 130 ret = ddr3_tip_bist_activate(dev_num, pattern, in hws_ddr3_run_bist() 141 ret = ddr3_tip_bist_activate(dev_num, pattern, in hws_ddr3_run_bist() [all …]
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/openbmc/linux/drivers/cdx/controller/ |
H A D | cdx_controller.c | 50 u8 bus_num, u8 dev_num, in cdx_configure_device() argument 57 ret = cdx_mcdi_reset_device(cdx->priv, bus_num, dev_num); in cdx_configure_device() 69 u8 bus_num, dev_num, num_cdx_bus; in cdx_scan_devices() local 93 for (dev_num = 0; dev_num < num_cdx_dev; dev_num++) { in cdx_scan_devices() 98 dev_num, &dev_params); in cdx_scan_devices() 102 bus_num, dev_num, ret); in cdx_scan_devices() 111 dev_num, ret); in cdx_scan_devices() 116 dev_num, bus_num); in cdx_scan_devices()
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H A D | mcdi_functions.c | 49 u8 bus_num, u8 dev_num, in cdx_mcdi_get_dev_config() argument 60 MCDI_SET_DWORD(inbuf, CDX_BUS_GET_DEVICE_CONFIG_IN_DEVICE, dev_num); in cdx_mcdi_get_dev_config() 71 dev_params->dev_num = dev_num; in cdx_mcdi_get_dev_config() 127 int cdx_mcdi_reset_device(struct cdx_mcdi *cdx, u8 bus_num, u8 dev_num) in cdx_mcdi_reset_device() argument 133 MCDI_SET_DWORD(inbuf, CDX_DEVICE_RESET_IN_DEVICE, dev_num); in cdx_mcdi_reset_device()
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/openbmc/linux/drivers/soundwire/ |
H A D | bus.c | 177 if (slave->dev_num) { /* clear dev_num if assigned */ in sdw_delete_slave() 178 clear_bit(slave->dev_num, bus->assigned); in sdw_delete_slave() 279 msg->dev_num, ret, in sdw_transfer_unlocked() 353 msg->dev_num, ret); in sdw_transfer_defer() 359 u32 addr, size_t count, u16 dev_num, u8 flags, u8 *buf) in sdw_fill_msg() argument 364 msg->dev_num = dev_num; in sdw_fill_msg() 383 if (dev_num == SDW_ENUM_DEV_NUM || dev_num == SDW_BROADCAST_DEV_NUM) { in sdw_fill_msg() 384 pr_err("SDW: Invalid device for paging :%d\n", dev_num); in sdw_fill_msg() 422 ret = sdw_fill_msg(&msg, slave, addr, size, slave->dev_num, flags, val); in sdw_ntransfer_no_pm() 483 sdw_bread_no_pm(struct sdw_bus *bus, u16 dev_num, u32 addr) in sdw_bread_no_pm() argument [all …]
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/openbmc/u-boot/include/ |
H A D | netdev.h | 29 int bcm_sf2_eth_register(bd_t *bis, u8 dev_num); 32 int cs8900_initialize(u8 dev_num, int base_addr); 40 int ep93xx_eth_initialize(u8 dev_num, int base_addr); 42 int ethoc_initialize(u8 dev_num, int base_addr); 49 int ks8851_mll_initialize(u8 dev_num, int base_addr); 50 int lan91c96_initialize(u8 dev_num, int base_addr); 68 int smc91111_initialize(u8 dev_num, int base_addr); 69 int smc911x_initialize(u8 dev_num, int base_addr);
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/openbmc/linux/tools/iio/ |
H A D | iio_generic_buffer.c | 360 int dev_num = -1, trig_num = -1; in main() local 424 dev_num = strtoul(optarg, &dummy, 10); in main() 455 if (dev_num < 0 && !device_name) { in main() 460 } else if (dev_num >= 0 && device_name) { in main() 465 } else if (dev_num < 0) { in main() 466 dev_num = find_type_by_name(device_name, "iio:device"); in main() 467 if (dev_num < 0) { in main() 469 ret = dev_num; in main() 473 printf("iio device number being used is %d\n", dev_num); in main() 475 ret = asprintf(&dev_dir_name, "%siio:device%d", iio_dir, dev_num); in main() [all …]
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/openbmc/u-boot/drivers/dfu/ |
H A D | dfu_mmc.c | 29 mmc = find_mmc_device(dfu->data.mmc.dev_num); in mmc_block_op() 31 pr_err("Device MMC %d - not found!", dfu->data.mmc.dev_num); in mmc_block_op() 53 dfu->data.mmc.dev_num, in mmc_block_op() 61 dfu->data.mmc.dev_num, blk_start, blk_count, buf); in mmc_block_op() 78 dfu->data.mmc.dev_num, in mmc_block_op() 85 dfu->data.mmc.dev_num, in mmc_block_op() 304 dfu->data.mmc.dev_num = simple_strtoul(devstr, NULL, 10); in dfu_fill_entity_mmc() 322 mmc = find_mmc_device(dfu->data.mmc.dev_num); in dfu_fill_entity_mmc() 325 dfu->data.mmc.dev_num); in dfu_fill_entity_mmc()
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/openbmc/linux/drivers/net/ethernet/marvell/prestera/ |
H A D | prestera_dsa.c | 86 u32 dev_num = dsa->hw_dev_num; in prestera_dsa_build() local 91 words[0] |= FIELD_PREP(PRESTERA_DSA_W0_DEV_NUM, dev_num); in prestera_dsa_build() 92 dev_num = FIELD_GET(PRESTERA_DSA_DEV_NUM, dev_num); in prestera_dsa_build() 93 words[3] |= FIELD_PREP(PRESTERA_DSA_W3_DEV_NUM, dev_num); in prestera_dsa_build()
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