1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0 */ 2f1df9364SStefan Roese /* 3f1df9364SStefan Roese * Copyright (C) Marvell International Ltd. and its affiliates 4f1df9364SStefan Roese */ 5f1df9364SStefan Roese 6f1df9364SStefan Roese #ifndef _DDR3_TRAINING_HW_ALGO_H_ 7f1df9364SStefan Roese #define _DDR3_TRAINING_HW_ALGO_H_ 8f1df9364SStefan Roese 9f1df9364SStefan Roese int ddr3_tip_vref(u32 dev_num); 10f1df9364SStefan Roese int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id); 11f1df9364SStefan Roese int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap); 12f1df9364SStefan Roese 13f1df9364SStefan Roese #endif /* _DDR3_TRAINING_HW_ALGO_H_ */ 14