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Searched refs:csrno (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcsr.c34 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) in riscv_get_csr_ops() argument
36 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; in riscv_get_csr_ops()
39 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) in riscv_set_csr_ops() argument
41 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; in riscv_set_csr_ops()
78 static RISCVException fs(CPURISCVState *env, int csrno) in fs() argument
93 static RISCVException vs(CPURISCVState *env, int csrno) in vs() argument
106 static RISCVException ctr(CPURISCVState *env, int csrno) in ctr() argument
115 if (rv32 && csrno >= CSR_CYCLEH) { in ctr()
119 ctr_index = csrno - base_csrno; in ctr()
122 if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || in ctr()
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H A Dth_csr.c31 int csrno; member
36 static RISCVException smode(CPURISCVState *env, int csrno) in smode() argument
54 static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, in read_th_sxstatus() argument
64 .csrno = CSR_TH_SXSTATUS,
73 int csrno = th_csr_list[i].csrno; in th_register_custom_csrs() local
76 riscv_set_csr_ops(csrno, csr_ops); in th_register_custom_csrs()
H A Dcpu.h778 RISCVException riscv_csrr(CPURISCVState *env, int csrno,
780 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
783 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
788 static inline void riscv_csr_write(CPURISCVState *env, int csrno, in riscv_csr_write() argument
791 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); in riscv_csr_write()
794 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) in riscv_csr_read() argument
797 riscv_csrrw(env, csrno, &val, 0, 0); in riscv_csr_read()
802 int csrno);
803 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
805 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
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H A Dcpu.c806 int csrno = dump_csrs[i]; in riscv_cpu_dump_state() local
808 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); in riscv_cpu_dump_state()
816 csr_ops[csrno].name, val); in riscv_cpu_dump_state()
855 int csrno = dump_rvv_csrs[i]; in riscv_cpu_dump_state() local
857 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); in riscv_cpu_dump_state()
865 csr_ops[csrno].name, val); in riscv_cpu_dump_state()
/openbmc/qemu/disas/
H A Driscv.c2261 static const char *csr_name(int csrno) in csr_name() argument
2263 switch (csrno) { in csr_name()