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Searched refs:csr (Results 1 – 25 of 278) sorted by relevance

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/openbmc/linux/arch/alpha/kernel/
H A Dcore_tsunami.c181 volatile unsigned long *csr; in tsunami_pci_tbi() local
186 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
188 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
194 *csr = value; in tsunami_pci_tbi()
196 *csr; in tsunami_pci_tbi()
227 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
231 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
232 int source = (TSUNAMI_cchip->misc.csr >> 29) & 7; in tsunami_probe_write()
233 TSUNAMI_cchip->misc.csr |= (1L << 28); /* ...and unlock NXS. */ in tsunami_probe_write()
251 if (tsunami_probe_read(&pchip->pctl.csr) == 0) in tsunami_init_one_pchip()
[all …]
H A Dcore_wildfire.c121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr = hose->sg_pci->dma_base | 3; in wildfire_init_hose()
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H A Dcore_titan.c207 volatile unsigned long *csr; in titan_pci_tbi() local
220 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
222 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
229 *csr = value; in titan_pci_tbi()
231 *csr; in titan_pci_tbi()
240 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
293 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
294 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
295 saved_config[index].tba[0] = port->tba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsba[1] = port->wsba[1].csr; in titan_init_one_pachip_port()
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H A Dsys_marvel.c96 ctl = &io7->csrs->PO7_LSI_CTL[irq & 0xff].csr; /* assume LSI */ in io7_get_irq_ctl()
98 ctl = &io7->csrs->PO7_MSI_CTL[((irq - 0x80) >> 5) & 0x0f].csr; in io7_get_irq_ctl()
174 volatile unsigned long *csr, in io7_redirect_irq() argument
179 val = *csr; in io7_redirect_irq()
183 *csr = val; in io7_redirect_irq()
185 *csr; in io7_redirect_irq()
196 val = io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
200 io7->csrs->PO7_LSI_CTL[which].csr = val; in io7_redirect_one_lsi()
202 io7->csrs->PO7_LSI_CTL[which].csr; in io7_redirect_one_lsi()
213 val = io7->csrs->PO7_MSI_CTL[which].csr; in io7_redirect_one_msi()
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/openbmc/qemu/hw/net/
H A Dpcnet.c65 #define CSR_INIT(S) !!(((S)->csr[0])&0x0001)
66 #define CSR_STRT(S) !!(((S)->csr[0])&0x0002)
67 #define CSR_STOP(S) !!(((S)->csr[0])&0x0004)
68 #define CSR_TDMD(S) !!(((S)->csr[0])&0x0008)
69 #define CSR_TXON(S) !!(((S)->csr[0])&0x0010)
70 #define CSR_RXON(S) !!(((S)->csr[0])&0x0020)
71 #define CSR_INEA(S) !!(((S)->csr[0])&0x0040)
72 #define CSR_BSWP(S) !!(((S)->csr[3])&0x0004)
73 #define CSR_LAPPEN(S) !!(((S)->csr[3])&0x0020)
74 #define CSR_DXSUFLO(S) !!(((S)->csr[3])&0x0040)
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H A Dtulip.c29 uint32_t csr[16]; member
53 VMSTATE_UINT32_ARRAY(csr, TULIPState, 16),
75 if (s->csr[0] & CSR0_DBO) { in tulip_desc_read()
93 if (s->csr[0] & CSR0_DBO) { in tulip_desc_write()
108 uint32_t ie = s->csr[5] & s->csr[7]; in tulip_update_int()
111 s->csr[5] &= ~(CSR5_AIS | CSR5_NIS); in tulip_update_int()
114 s->csr[5] |= CSR5_NIS; in tulip_update_int()
120 s->csr[5] |= CSR5_AIS; in tulip_update_int()
123 assert = s->csr[5] & s->csr[7] & (CSR5_AIS | CSR5_NIS); in tulip_update_int()
124 trace_tulip_irq(s->csr[5], s->csr[7], assert ? "assert" : "deassert"); in tulip_update_int()
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/openbmc/linux/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hw_20_comp.h23 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr) in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER() argument
27 QAT_FIELD_SET(val32, csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
30 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
36 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
39 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
42 QAT_FIELD_SET(val32, csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
45 QAT_FIELD_SET(val32, csr.hash_col, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
48 QAT_FIELD_SET(val32, csr.hash_update, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
51 QAT_FIELD_SET(val32, csr.skip_ctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
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/openbmc/u-boot/drivers/usb/musb/
H A Dmusb_hcd.c40 u16 csr; in write_toggle() local
43 csr = readw(&musbr->txcsr); in write_toggle()
45 if (csr & MUSB_TXCSR_MODE) in write_toggle()
46 csr = MUSB_TXCSR_CLRDATATOG; in write_toggle()
48 csr = 0; in write_toggle()
49 writew(csr, &musbr->txcsr); in write_toggle()
51 csr |= MUSB_TXCSR_H_WR_DATATOGGLE; in write_toggle()
52 writew(csr, &musbr->txcsr); in write_toggle()
53 csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); in write_toggle()
54 writew(csr, &musbr->txcsr); in write_toggle()
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/openbmc/linux/arch/sparc/kernel/
H A Debus.c74 u32 csr = 0; in ebus_dma_irq() local
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
99 u32 csr; in ebus_dma_register() local
113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
118 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
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/openbmc/u-boot/arch/riscv/include/asm/
H A Dcsr.h64 #define xcsr(csr) #csr argument
66 #define csr_swap(csr, val) \ argument
69 __asm__ __volatile__ ("csrrw %0, " xcsr(csr) ", %1" \
75 #define csr_read(csr) \ argument
78 __asm__ __volatile__ ("csrr %0, " xcsr(csr) \
84 #define csr_write(csr, val) \ argument
87 __asm__ __volatile__ ("csrw " xcsr(csr) ", %0" \
92 #define csr_read_set(csr, val) \ argument
95 __asm__ __volatile__ ("csrrs %0, " xcsr(csr) ", %1" \
101 #define csr_set(csr, val) \ argument
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/openbmc/linux/drivers/usb/musb/
H A Dmusb_gadget.c229 u16 fifo_count = 0, csr; in txstate() local
248 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
254 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
256 musb_ep->end_point.name, csr); in txstate()
260 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
262 musb_ep->end_point.name, csr); in txstate()
268 csr); in txstate()
301 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
303 musb_writew(epio, MUSB_TXCSR, csr in txstate()
305 csr &= ~MUSB_TXCSR_DMAMODE; in txstate()
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H A Dmusb_gadget_ep0.c243 u16 csr; in service_zero_data_request() local
266 csr = musb_readw(regs, MUSB_TXCSR); in service_zero_data_request()
267 csr |= MUSB_TXCSR_CLRDATATOG | in service_zero_data_request()
269 csr &= ~(MUSB_TXCSR_P_SENDSTALL | in service_zero_data_request()
272 musb_writew(regs, MUSB_TXCSR, csr); in service_zero_data_request()
274 csr = musb_readw(regs, MUSB_RXCSR); in service_zero_data_request()
275 csr |= MUSB_RXCSR_CLRDATATOG | in service_zero_data_request()
277 csr &= ~(MUSB_RXCSR_P_SENDSTALL | in service_zero_data_request()
279 musb_writew(regs, MUSB_RXCSR, csr); in service_zero_data_request()
403 u16 csr; in service_zero_data_request() local
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/openbmc/linux/drivers/crypto/starfive/
H A Djh7110-rsa.c99 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
101 writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET); in starfive_rsa_montgomery_form()
107 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
108 rctx->csr.pka.cln_done = 1; in starfive_rsa_montgomery_form()
109 rctx->csr.pka.opsize = opsize; in starfive_rsa_montgomery_form()
110 rctx->csr.pka.exposize = opsize; in starfive_rsa_montgomery_form()
111 rctx->csr.pka.cmd = CRYPTO_CMD_PRE; in starfive_rsa_montgomery_form()
112 rctx->csr.pka.start = 1; in starfive_rsa_montgomery_form()
113 rctx->csr.pka.not_r2 = 1; in starfive_rsa_montgomery_form()
114 rctx->csr.pka.ie = 1; in starfive_rsa_montgomery_form()
[all …]
/openbmc/u-boot/drivers/usb/musb-new/
H A Dmusb_gadget.c319 u16 fifo_count = 0, csr; in txstate() local
338 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
344 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
346 musb_ep->end_point.name, csr); in txstate()
350 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
352 musb_ep->end_point.name, csr); in txstate()
358 csr); in txstate()
392 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
394 musb_writew(epio, MUSB_TXCSR, csr in txstate()
396 csr &= ~MUSB_TXCSR_DMAMODE; in txstate()
[all …]
H A Dmusb_gadget_ep0.c245 u16 csr; in service_zero_data_request() local
268 csr = musb_readw(regs, MUSB_TXCSR); in service_zero_data_request()
269 csr |= MUSB_TXCSR_CLRDATATOG | in service_zero_data_request()
271 csr &= ~(MUSB_TXCSR_P_SENDSTALL | in service_zero_data_request()
274 musb_writew(regs, MUSB_TXCSR, csr); in service_zero_data_request()
276 csr = musb_readw(regs, MUSB_RXCSR); in service_zero_data_request()
277 csr |= MUSB_RXCSR_CLRDATATOG | in service_zero_data_request()
279 csr &= ~(MUSB_RXCSR_P_SENDSTALL | in service_zero_data_request()
281 musb_writew(regs, MUSB_RXCSR, csr); in service_zero_data_request()
409 u16 csr; in service_zero_data_request() local
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H A Dmusb_host.c93 u16 csr; in musb_h_tx_flush_fifo() local
97 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
98 while (csr & MUSB_TXCSR_FIFONOTEMPTY) { in musb_h_tx_flush_fifo()
99 if (csr != lastcsr) in musb_h_tx_flush_fifo()
100 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr); in musb_h_tx_flush_fifo()
101 lastcsr = csr; in musb_h_tx_flush_fifo()
102 csr |= MUSB_TXCSR_FLUSHFIFO; in musb_h_tx_flush_fifo()
103 musb_writew(epio, MUSB_TXCSR, csr); in musb_h_tx_flush_fifo()
104 csr = musb_readw(epio, MUSB_TXCSR); in musb_h_tx_flush_fifo()
107 ep->epnum, csr)) in musb_h_tx_flush_fifo()
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/openbmc/linux/drivers/scsi/
H A Dsun3_scsi.c73 unsigned short csr; /* control/status reg */ member
196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
200 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr()
203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
204 if (csr & CSR_DMA_BUSERR) in scsi_sun3_intr()
206 if (csr & CSR_DMA_CONFLICT) in scsi_sun3_intr()
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr()
242 dregs->csr &= ~CSR_FIFO; in sun3scsi_dma_setup()
243 dregs->csr |= CSR_FIFO; in sun3scsi_dma_setup()
248 dregs->csr |= CSR_SEND; in sun3scsi_dma_setup()
[all …]
/openbmc/linux/drivers/watchdog/
H A Dshwdt.c85 u8 csr; in sh_wdt_start() local
95 csr = sh_wdt_read_csr(); in sh_wdt_start()
96 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
97 sh_wdt_write_csr(csr); in sh_wdt_start()
109 csr = sh_wdt_read_csr(); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
115 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
116 csr &= ~RSTCSR_RSTS; in sh_wdt_start()
[all …]
/openbmc/u-boot/drivers/usb/gadget/
H A Dat91_udc.c125 u32 csr; in read_fifo() local
137 csr = __raw_readl(creg); in read_fifo()
138 if ((csr & RX_DATA_READY) == 0) in read_fifo()
141 count = (csr & AT91_UDP_RXBYTECNT) >> 16; in read_fifo()
152 csr |= CLR_FX; in read_fifo()
155 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
158 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK1); in read_fifo()
162 csr &= ~(SET_FX | AT91_UDP_RX_DATA_BK0); in read_fifo()
163 __raw_writel(csr, creg); in read_fifo()
185 csr = __raw_readl(creg); in read_fifo()
[all …]
/openbmc/linux/arch/sh/kernel/cpu/
H A Dadc.c16 unsigned char csr; in adc_single() local
22 csr = __raw_readb(ADCSR); in adc_single()
23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
24 __raw_writeb(csr, ADCSR); in adc_single()
27 csr = __raw_readb(ADCSR); in adc_single()
28 } while ((csr & ADCSR_ADF) == 0); in adc_single()
30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()
/openbmc/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_privileged.c.inc8 #include "cpu-csr.h"
165 const CSRInfo *csr;
170 csr = &csr_info[csr_num];
171 if (csr->offset == 0) {
174 return csr;
177 static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write)
179 if ((csr->flags & CSRFL_READONLY) && write) {
182 if ((csr->flags & CSRFL_IO) && translator_io_start(&ctx->base)) {
184 } else if ((csr->flags & CSRFL_EXITTB) && write) {
193 const CSRInfo *csr;
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/openbmc/linux/drivers/usb/gadget/udc/
H A Dat91_udc.c111 u32 csr; in proc_ep_show() local
118 csr = __raw_readl(ep->creg); in proc_ep_show()
132 csr, in proc_ep_show()
133 (csr & 0x07ff0000) >> 16, in proc_ep_show()
134 (csr & (1 << 15)) ? "enabled" : "disabled", in proc_ep_show()
135 (csr & (1 << 11)) ? "DATA1" : "DATA0", in proc_ep_show()
136 types[(csr & 0x700) >> 8], in proc_ep_show()
139 (!(csr & 0x700)) in proc_ep_show()
140 ? ((csr & (1 << 7)) ? " IN" : " OUT") in proc_ep_show()
142 (csr & (1 << 6)) ? " rxdatabk1" : "", in proc_ep_show()
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/openbmc/linux/sound/soc/intel/atom/sst/
H A Dsst_loader.c56 union config_status_reg_mrfld csr; in intel_sst_reset_dsp_mrfld() local
59 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
61 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
63 csr.full |= 0x7; in intel_sst_reset_dsp_mrfld()
64 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
65 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
67 dev_dbg(sst_drv_ctx->dev, "value:0x%llx\n", csr.full); in intel_sst_reset_dsp_mrfld()
69 csr.full &= ~(0x1); in intel_sst_reset_dsp_mrfld()
70 sst_shim_write64(sst_drv_ctx->shim, SST_CSR, csr.full); in intel_sst_reset_dsp_mrfld()
72 csr.full = sst_shim_read64(sst_drv_ctx->shim, SST_CSR); in intel_sst_reset_dsp_mrfld()
[all …]
/openbmc/linux/arch/riscv/kvm/
H A Daia.c71 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_flush_interrupts() local
81 csr->hviph &= ~mask; in kvm_riscv_vcpu_aia_flush_interrupts()
82 csr->hviph |= val; in kvm_riscv_vcpu_aia_flush_interrupts()
88 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_sync_interrupts() local
91 csr->vsieh = csr_read(CSR_VSIEH); in kvm_riscv_vcpu_aia_sync_interrupts()
125 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_aia_update_hvip() local
133 aia_set_hvictl(!!(csr->hvip & BIT(IRQ_VS_EXT))); in kvm_riscv_vcpu_aia_update_hvip()
138 struct kvm_vcpu_aia_csr *csr = &vcpu->arch.aia_context.guest_csr; in kvm_riscv_vcpu_aia_load() local
143 csr_write(CSR_VSISELECT, csr->vsiselect); in kvm_riscv_vcpu_aia_load()
144 csr_write(CSR_HVIPRIO1, csr->hviprio1); in kvm_riscv_vcpu_aia_load()
[all …]
H A Dvcpu.c20 #include <asm/csr.h>
47 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_reset_vcpu() local
65 memcpy(csr, reset_csr, sizeof(*csr)); in kvm_riscv_reset_vcpu()
324 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_flush_interrupts()
331 csr->hvip &= ~mask; in kvm_riscv_vcpu_flush_interrupts()
332 csr->hvip |= val; in kvm_riscv_vcpu_flush_interrupts()
343 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; in kvm_riscv_vcpu_sync_interrupts()
346 csr->vsie = csr_read(CSR_VSIE); in kvm_riscv_vcpu_sync_interrupts()
350 if ((csr in kvm_riscv_vcpu_sync_interrupts()
322 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; kvm_riscv_vcpu_flush_interrupts() local
341 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; kvm_riscv_vcpu_sync_interrupts() local
498 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; kvm_arch_vcpu_load() local
530 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; kvm_arch_vcpu_put() local
603 struct kvm_vcpu_csr *csr = &vcpu->arch.guest_csr; kvm_riscv_update_hvip() local
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