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Searched refs:crn (Results 1 – 25 of 44) sorted by relevance

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/openbmc/qemu/target/arm/
H A Dhelper.c634 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
639 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
651 .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
659 .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
673 .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
682 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
684 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
686 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
688 { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
691 { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
[all …]
H A Dcortex-regs.c31 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
35 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
39 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
42 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
45 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
48 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
54 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
60 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
66 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
H A Ddebug_helper.c948 { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
952 .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
955 { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
960 .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
971 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 1, .opc2 = 0,
981 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2,
985 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
990 .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0,
999 .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
1009 .cp = 14, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
[all …]
H A Dsyndrome.h163 int crn, int crm, int rt, in syn_aa64_sysregtrap() argument
167 | (op0 << 20) | (op2 << 17) | (op1 << 14) | (crn << 10) | (rt << 5) in syn_aa64_sysregtrap()
172 int crn, int crm, int rt, int isread, in syn_cp14_rt_trap() argument
178 | (crn << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp14_rt_trap()
182 int crn, int crm, int rt, int isread, in syn_cp15_rt_trap() argument
188 | (crn << 10) | (rt << 5) | (crm << 1) | isread; in syn_cp15_rt_trap()
H A Dcpregs.h171 #define ENCODE_CP_REG(cp, is64, ns, crn, crm, opc1, opc2) \ argument
173 ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2))
175 #define ENCODE_AA64_CP_REG(cp, crn, crm, op0, op1, op2) \ argument
180 ((crn) << CP_REG_ARM64_SYSREG_CRN_SHIFT) | \
860 uint8_t crn; member
1078 uint8_t crn, uint8_t crm) in arm_cpreg_encoding_in_idspace() argument
1081 crn == 0 && crm < 8; in arm_cpreg_encoding_in_idspace()
1092 ri->crn, ri->crm); in arm_cpreg_in_idspace()
/openbmc/qemu/target/arm/tcg/
H A Dcpu64.c481 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 7, .opc2 = 0,
486 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 0,
489 .opc0 = 3, .opc1 = 6, .crn = 15, .crm = 7, .opc2 = 0,
492 .opc0 = 3, .opc1 = 5, .crn = 15, .crm = 7, .opc2 = 0,
495 .opc0 = 3, .opc1 = 4, .crn = 15, .crm = 7, .opc2 = 1,
498 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 0,
502 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 1,
506 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 2,
514 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0,
517 .opc0 = 3, .opc1 = 0, .crn = 15, .crm = 1, .opc2 = 4,
[all …]
H A Dcpu32.c197 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1, in arm1026_initfn()
337 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
339 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
388 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
391 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
394 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
397 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
400 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
402 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
404 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
[all …]
/openbmc/qemu/target/arm/hvf/
H A Dtrace-events1 …0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg read at pc=0x%"PRIx64…
2 …0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2) "unhandled sysreg write at pc=0x%"PRIx6…
6 …t32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg read 0x%0…
7 …32_t op0, uint32_t op1, uint32_t crn, uint32_t crm, uint32_t op2, uint64_t val) "sysreg write 0x%0…
/openbmc/qemu/hw/intc/
H A Darm_gicv3_cpuif.c2443 .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 6, .opc2 = 0,
2455 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 0,
2461 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 1,
2467 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 2,
2473 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 3,
2480 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 8, .opc2 = 4,
2488 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 9, .opc2 = 0,
2495 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 1,
2501 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 3,
2507 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 11, .opc2 = 5,
[all …]
H A Darm_gicv3_kvm.c51 #define KVM_DEV_ARM_VGIC_SYSREG(op0, op1, crn, crm, op2) \ argument
54 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
734 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 12, .opc2 = 4,
/openbmc/linux/arch/arm64/tools/
H A Dgen-sysreg.awk156 crn = $5
164 define("REG_" reg, "S" op0 "_" op1 "_C" crn "_C" crm "_" op2)
165 define("SYS_" reg, "sys_reg(" op0 ", " op1 ", " crn ", " crm ", " op2 ")")
169 define("SYS_" reg "_CRn", crn)
196 crn = null
/openbmc/linux/drivers/scsi/fnic/
H A Dfcpio.h199 u8 crn; /* SCSI Command Reference No. */ member
247 u8 crn; /* SCSI Command Reference No. */ member
521 u8 crn; /* SCSI Command Reference No. */ member
554 u8 crn; /* SCSI Command Reference No. */ member
585 u8 crn; /* SCSI Command Reference No. */ member
H A Dfnic_res.h72 u8 crn, u8 pri_ta, in fnic_queue_wq_copy_desc_icmnd_16() argument
95 desc->u.icmnd_16.crn = crn; /* SCSI Command Reference No.*/ in fnic_queue_wq_copy_desc_icmnd_16()
/openbmc/linux/arch/arm64/include/asm/
H A Desr.h212 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ argument
216 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
328 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ argument
331 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
/openbmc/linux/include/uapi/linux/
H A Dvirtio_scsi.h49 __u8 crn; member
59 __u8 crn; member
/openbmc/qemu/include/standard-headers/linux/
H A Dvirtio_scsi.h49 uint8_t crn; member
59 uint8_t crn; member
/openbmc/qemu/linux-headers/asm-arm64/
H A Dkvm.h249 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
253 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
513 #define KVM_ARM_FEATURE_ID_RANGE_IDX(op0, op1, crn, crm, op2) \ argument
/openbmc/linux/tools/arch/arm/include/uapi/asm/
H A Dkvm.h166 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
169 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
/openbmc/qemu/linux-headers/asm-arm/
H A Dkvm.h166 #define __ARM_CP15_REG(op1,crn,crm,op2) \ argument
169 ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
/openbmc/qemu/pc-bios/s390-ccw/
H A Dvirtio-scsi.h41 uint8_t crn; /* = 0 */ member
/openbmc/linux/tools/arch/arm64/include/uapi/asm/
H A Dkvm.h246 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
250 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
/openbmc/linux/arch/arm64/include/uapi/asm/
H A Dkvm.h246 #define __ARM64_SYS_REG(op0,op1,crn,crm,op2) \ argument
250 ARM64_SYS_REG_SHIFT_MASK(crn, CRN) | \
/openbmc/linux/tools/testing/selftests/kvm/aarch64/
H A Dget-reg-list.c185 unsigned op0, op1, crn, crm, op2; in print_reg() local
237 crn = (id & KVM_REG_ARM64_SYSREG_CRN_MASK) >> KVM_REG_ARM64_SYSREG_CRN_SHIFT; in print_reg()
240 TEST_ASSERT(id == ARM64_SYS_REG(op0, op1, crn, crm, op2), in print_reg()
242 printf("\tARM64_SYS_REG(%d, %d, %d, %d, %d),\n", op0, op1, crn, crm, op2); in print_reg()
/openbmc/linux/arch/arm/include/asm/hardware/
H A Dcp14.h17 #define MRC14(op1, crn, crm, op2) \ argument
20 asm volatile("mrc p14, "#op1", %0, "#crn", "#crm", "#op2 : "=r" (val)); \
24 #define MCR14(val, op1, crn, crm, op2) \ argument
26 asm volatile("mcr p14, "#op1", %0, "#crn", "#crm", "#op2 : : "r" (val));\
/openbmc/qemu/target/ppc/
H A Dtranslate.c4042 uint32_t crm, crn; in gen_mfcr() local
4047 crn = ctz32(crm); in gen_mfcr()
4048 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]); in gen_mfcr()
4050 cpu_gpr[rD(ctx->opcode)], crn * 4); in gen_mfcr()
4156 uint32_t crm, crn; in gen_mtcrf() local
4162 crn = ctz32(crm); in gen_mtcrf()
4164 tcg_gen_shri_i32(temp, temp, crn * 4); in gen_mtcrf()
4165 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf); in gen_mtcrf()
4170 for (crn = 0 ; crn < 8 ; crn++) { in gen_mtcrf()
4171 if (crm & (1 << crn)) { in gen_mtcrf()
[all …]

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