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Searched refs:crlapb_base (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/board/xilinx/versal/
H A Dboard.c30 readl(&crlapb_base->iou_switch_ctrl)); in board_early_init_r()
34 &crlapb_base->iou_switch_ctrl); in board_early_init_r()
37 val = readl(&crlapb_base->timestamp_ref_ctrl); in board_early_init_r()
39 writel(val, &crlapb_base->timestamp_ref_ctrl); in board_early_init_r()
42 readl(&crlapb_base->timestamp_ref_ctrl)); in board_early_init_r()
45 writel(0, &crlapb_base->rst_timestamp); in board_early_init_r()
/openbmc/u-boot/arch/arm/mach-zynqmp/
H A Dspl.c40 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()
44 &crlapb_base->boot_pin_ctrl); in ps_mode_reset()
72 &crlapb_base->boot_mode); in spl_boot_device()
75 reg = readl(&crlapb_base->boot_mode); in spl_boot_device()
H A Dmp.c97 tmp = readl(&crlapb_base->rst_lpd_top); in set_r5_reset()
104 writel(tmp, &crlapb_base->rst_lpd_top); in set_r5_reset()
111 tmp = readl(&crlapb_base->rst_lpd_top); in release_r5_reset()
118 writel(tmp, &crlapb_base->rst_lpd_top); in release_r5_reset()
125 tmp = readl(&crlapb_base->cpu_r5_ctrl); in enable_clock_r5()
127 writel(tmp, &crlapb_base->cpu_r5_ctrl); in enable_clock_r5()
158 u32 val = readl(&crlapb_base->rst_lpd_top); in cpu_status()
/openbmc/u-boot/arch/arm/mach-versal/
H A Dmp.c71 tmp = readl(&crlapb_base->rst_cpu_r5); in release_r5_reset()
79 writel(tmp, &crlapb_base->rst_cpu_r5); in release_r5_reset()
86 tmp = readl(&crlapb_base->cpu_r5_ctrl); in enable_clock_r5()
88 writel(tmp, &crlapb_base->cpu_r5_ctrl); in enable_clock_r5()
/openbmc/u-boot/board/xilinx/zynqmp/
H A Dzynqmp.c388 val = readl(&crlapb_base->timestamp_ref_ctrl); in board_early_init_r()
392 val = readl(&crlapb_base->timestamp_ref_ctrl); in board_early_init_r()
394 writel(val, &crlapb_base->timestamp_ref_ctrl); in board_early_init_r()
491 ret = readl(&crlapb_base->reset_reason); in reset_reason()
507 writel(~0, &crlapb_base->reset_reason); in reset_reason()
568 ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, &reg); in board_late_init()
/openbmc/u-boot/arch/arm/mach-versal/include/mach/
H A Dhardware.h26 #define crlapb_base ((struct crlapb_regs *)VERSAL_CRL_APB_BASEADDR) macro
/openbmc/u-boot/arch/arm/mach-zynqmp/include/mach/
H A Dhardware.h49 #define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR) macro