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Searched refs:cpuclk (Results 1 – 25 of 36) sorted by relevance

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/openbmc/linux/drivers/clk/rockchip/
H A Dclk-cpu.c68 struct rockchip_cpuclk *cpuclk, unsigned long rate) in rockchip_get_cpuclk_settings() argument
71 cpuclk->rate_table; in rockchip_get_cpuclk_settings()
74 for (i = 0; i < cpuclk->rate_count; i++) { in rockchip_get_cpuclk_settings()
85 struct rockchip_cpuclk *cpuclk = to_rockchip_cpuclk_hw(hw); in rockchip_cpuclk_recalc_rate() local
86 const struct rockchip_cpuclk_reg_data *reg_data = cpuclk->reg_data; in rockchip_cpuclk_recalc_rate()
87 u32 clksel0 = readl_relaxed(cpuclk->reg_base + reg_data->core_reg[0]); in rockchip_cpuclk_recalc_rate()
98 static void rockchip_cpuclk_set_dividers(struct rockchip_cpuclk *cpuclk, in rockchip_cpuclk_set_dividers() argument
112 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_dividers()
116 static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk, in rockchip_cpuclk_set_pre_muxs() argument
130 writel(clksel->val, cpuclk->reg_base + clksel->reg); in rockchip_cpuclk_set_pre_muxs()
[all …]
/openbmc/linux/drivers/clk/mvebu/
H A Dclk-cpu.c51 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_recalc_rate() local
54 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_recalc_rate()
55 div = (reg >> (cpuclk->cpu * 8)) & SYS_CTRL_CLK_DIVIDER_MASK; in clk_cpu_recalc_rate()
78 struct cpu_clk *cpuclk = to_cpu_clk(hwclk); in clk_cpu_off_set_rate() local
83 reg = (readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET) in clk_cpu_off_set_rate()
84 & (~(SYS_CTRL_CLK_DIVIDER_MASK << (cpuclk->cpu * 8)))) in clk_cpu_off_set_rate()
85 | (div << (cpuclk->cpu * 8)); in clk_cpu_off_set_rate()
86 writel(reg, cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET); in clk_cpu_off_set_rate()
88 reload_mask = 1 << (20 + cpuclk->cpu); in clk_cpu_off_set_rate()
90 reg = readl(cpuclk->reg_base + SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET) in clk_cpu_off_set_rate()
[all …]
/openbmc/linux/drivers/clk/samsung/
H A Dclk-cpu.c150 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_pre_rate_change() argument
152 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_pre_rate_change()
153 unsigned long alt_prate = clk_hw_get_rate(cpuclk->alt_parent); in exynos_cpuclk_pre_rate_change()
165 spin_lock_irqsave(cpuclk->lock, flags); in exynos_cpuclk_pre_rate_change()
173 if (cpuclk->flags & CLK_CPU_HAS_DIV1) { in exynos_cpuclk_pre_rate_change()
194 if (cpuclk->flags & CLK_CPU_NEEDS_DEBUG_ALT_DIV) { in exynos_cpuclk_pre_rate_change()
215 if (cpuclk->flags & CLK_CPU_HAS_DIV1) { in exynos_cpuclk_pre_rate_change()
221 spin_unlock_irqrestore(cpuclk->lock, flags); in exynos_cpuclk_pre_rate_change()
227 struct exynos_cpuclk *cpuclk, void __iomem *base) in exynos_cpuclk_post_rate_change() argument
229 const struct exynos_cpuclk_cfg_data *cfg_data = cpuclk->cfg; in exynos_cpuclk_post_rate_change()
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dsh-cpufreq.c47 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in __sh_cpufreq_target() local
58 freq = clk_round_rate(cpuclk, target->freq * 1000); in __sh_cpufreq_target()
70 clk_set_rate(cpuclk, freq); in __sh_cpufreq_target()
91 struct clk *cpuclk = &per_cpu(sh_cpuclk, policy->cpu); in sh_cpufreq_verify() local
94 freq_table = cpuclk->nr_freqs ? cpuclk->freq_table : NULL; in sh_cpufreq_verify()
100 policy->min = (clk_round_rate(cpuclk, 1) + 500) / 1000; in sh_cpufreq_verify()
101 policy->max = (clk_round_rate(cpuclk, ~0UL) + 500) / 1000; in sh_cpufreq_verify()
110 struct clk *cpuclk = &per_cpu(sh_cpuclk, cpu); in sh_cpufreq_cpu_init() local
116 cpuclk = clk_get(dev, "cpu_clk"); in sh_cpufreq_cpu_init()
117 if (IS_ERR(cpuclk)) { in sh_cpufreq_cpu_init()
[all …]
/openbmc/linux/arch/mips/txx9/generic/
H A Dsetup_tx4927.c92 unsigned int cpuclk = 0; in tx4927_setup() local
126 cpuclk = txx9_gbus_clock * 2; break; in tx4927_setup()
129 cpuclk = txx9_gbus_clock * 5 / 2; break; in tx4927_setup()
132 cpuclk = txx9_gbus_clock * 3; break; in tx4927_setup()
135 cpuclk = txx9_gbus_clock * 4; break; in tx4927_setup()
137 txx9_cpu_clock = cpuclk; in tx4927_setup()
142 cpuclk = txx9_cpu_clock; in tx4927_setup()
147 txx9_gbus_clock = cpuclk / 2; break; in tx4927_setup()
150 txx9_gbus_clock = cpuclk * 2 / 5; break; in tx4927_setup()
153 txx9_gbus_clock = cpuclk / 3; break; in tx4927_setup()
[all …]
H A Dsetup_tx4938.c97 unsigned int cpuclk = 0; in tx4938_setup() local
132 cpuclk = txx9_gbus_clock * 2; break; in tx4938_setup()
135 cpuclk = txx9_gbus_clock * 5 / 2; break; in tx4938_setup()
138 cpuclk = txx9_gbus_clock * 3; break; in tx4938_setup()
141 cpuclk = txx9_gbus_clock * 4; break; in tx4938_setup()
144 cpuclk = txx9_gbus_clock * 9 / 2; break; in tx4938_setup()
146 txx9_cpu_clock = cpuclk; in tx4938_setup()
151 cpuclk = txx9_cpu_clock; in tx4938_setup()
156 txx9_gbus_clock = cpuclk / 2; break; in tx4938_setup()
159 txx9_gbus_clock = cpuclk * 2 / 5; break; in tx4938_setup()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt9 1 = cpuclk (CPU clock)
16 1 = cpuclk (CPU clock)
22 1 = cpuclk (CPU clock)
28 1 = cpuclk (CPU clock)
36 1 = cpuclk (CPU clock)
42 1 = cpuclk (CPU0 clock)
48 1 = cpuclk (CPU0 clock)
72 output names ("tclk", "cpuclk", "l2clk", "ddrclk")
H A Dmvebu-cpu-clock.txt12 cpuclk: clock-complex@d0018700 {
22 clocks = <&cpuclk 0>;
/openbmc/linux/arch/mips/cavium-octeon/
H A Doct_ilm.c33 u64 cpuclk, avg, max, min; in oct_ilm_show() local
36 cpuclk = octeon_get_clock_rate(); in oct_ilm_show()
38 max = (curr_li.max_latency * 1000000000) / cpuclk; in oct_ilm_show()
39 min = (curr_li.min_latency * 1000000000) / cpuclk; in oct_ilm_show()
40 avg = (curr_li.latency_sum * 1000000000) / (cpuclk * curr_li.interrupt_cnt); in oct_ilm_show()
/openbmc/qemu/hw/mips/
H A Dmipssim.c149 Clock *cpuclk; in mips_mipssim_init() local
155 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); in mips_mipssim_init()
157 clock_set_hz(cpuclk, 6000000); /* 6 MHz */ in mips_mipssim_init()
159 clock_set_hz(cpuclk, 12000000); /* 12 MHz */ in mips_mipssim_init()
163 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, in mips_mipssim_init()
H A Dfuloong2e.c223 Clock *cpuclk; in mips_fuloong2e_init() local
228 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); in mips_fuloong2e_init()
229 clock_set_hz(cpuclk, 533080000); /* ~533 MHz */ in mips_fuloong2e_init()
232 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); in mips_fuloong2e_init()
H A Djazz.c174 Clock *cpuclk; in mips_jazz_init() local
210 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); in mips_jazz_init()
211 clock_set_hz(cpuclk, ext_clk[jazz_model].freq_hz in mips_jazz_init()
215 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, in mips_jazz_init()
H A Dloongson3_virt.c488 Clock *cpuclk; in mips_loongson3_virt_init() local
561 cpuclk = clock_new(OBJECT(machine), "cpu-refclk"); in mips_loongson3_virt_init()
562 clock_set_hz(cpuclk, DEF_LOONGSON3_FREQ); in mips_loongson3_virt_init()
570 cpu = mips_cpu_create_with_clock(machine->cpu_type, cpuclk, false); in mips_loongson3_virt_init()
/openbmc/linux/drivers/clk/qcom/
H A Dclk-cpu-8996.c277 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); in clk_cpu_8996_pmux_get_parent() local
280 regmap_read(clkr->regmap, cpuclk->reg, &val); in clk_cpu_8996_pmux_get_parent()
288 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_hw(hw); in clk_cpu_8996_pmux_set_parent() local
293 return regmap_update_bits(clkr->regmap, cpuclk->reg, PMUX_MASK, val); in clk_cpu_8996_pmux_set_parent()
549 struct clk_cpu_8996_pmux *cpuclk = to_clk_cpu_8996_pmux_nb(nb); in cpu_clk_notifier_cb() local
554 qcom_cpu_clk_msm8996_acd_init(cpuclk->clkr.regmap); in cpu_clk_notifier_cb()
566 clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, SMUX_INDEX); in cpu_clk_notifier_cb()
573 clk_cpu_8996_pmux_set_parent(&cpuclk->clkr.hw, ACD_INDEX); in cpu_clk_notifier_cb()
/openbmc/qemu/hw/timer/
H A Darmv7m_systick.c40 ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1); in systick_set_period_from_clock()
226 ptimer_set_period_from_clock(s->ptimer, s->cpuclk, 1); in systick_cpuclk_update()
254 s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", in systick_instance_init()
267 if (!clock_has_source(s->cpuclk)) { in systick_realize()
280 VMSTATE_CLOCK(cpuclk, SysTickState),
/openbmc/u-boot/arch/mips/mach-ath79/ar934x/
H A Dclk.c263 u32 cpuclk, ddrclk, busclk; in ar934x_update_clock() local
276 cpuclk = ar934x_get_xtal(); in ar934x_update_clock()
278 cpuclk = cpupll; in ar934x_update_clock()
280 cpuclk = ddrpll; in ar934x_update_clock()
303 gd->cpu_clk = cpuclk / (cpudiv + 1); in ar934x_update_clock()
/openbmc/u-boot/board/menlo/m53menlo/
H A Dm53menlo.c425 u32 cpuclk; in m53_set_clock() local
432 cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800; in m53_set_clock()
434 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); in m53_set_clock()
436 printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk); in m53_set_clock()
/openbmc/qemu/hw/arm/
H A Darmv7m.c277 s->cpuclk = qdev_init_clock_in(DEVICE(obj), "cpuclk", NULL, NULL, 0); in armv7m_instance_init()
293 if (!clock_has_source(s->cpuclk)) { in armv7m_realize()
461 qdev_connect_clock_in(DEVICE(&s->systick[M_REG_NS]), "cpuclk", s->cpuclk); in armv7m_realize()
482 s->cpuclk); in armv7m_realize()
564 VMSTATE_CLOCK(cpuclk, ARMv7MState),
/openbmc/qemu/include/hw/timer/
H A Darmv7m_systick.h47 Clock *cpuclk; member
/openbmc/linux/arch/arm/boot/dts/sigmastar/
H A Dmstar-infinity2m.dtsi30 clock-names = "cpuclk";
/openbmc/qemu/include/hw/arm/
H A Darmv7m.h96 Clock *cpuclk; member
/openbmc/linux/arch/arm/boot/dts/marvell/
H A Darmada-xp-mv78460.dtsi35 clocks = <&cpuclk 0>;
43 clocks = <&cpuclk 1>;
51 clocks = <&cpuclk 2>;
59 clocks = <&cpuclk 3>;
H A Darmada-xp-98dx3336.dtsi22 clocks = <&cpuclk 1>;
H A Darmada-xp-98dx4251.dtsi22 clocks = <&cpuclk 1>;
/openbmc/u-boot/board/inversepath/usbarmory/
H A Dusbarmory.c370 const uint32_t cpuclk = CPU_CLOCK; in set_clock() local
374 ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK); in set_clock()
376 printf("CPU: Switch CPU clock to %dMHZ failed\n", cpuclk); in set_clock()

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