1ab8ba01bSGregory CLEMENTDevice Tree Clock bindings for cpu clock of Marvell EBU platforms 2ab8ba01bSGregory CLEMENT 3ab8ba01bSGregory CLEMENTRequired properties: 4ab8ba01bSGregory CLEMENT- compatible : shall be one of the following: 5ab8ba01bSGregory CLEMENT "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP 6*e120c17aSChris Packham "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC 7ee2d8ea1SThomas Petazzoni- reg : Address and length of the clock complex register set, followed 8ee2d8ea1SThomas Petazzoni by address and length of the PMU DFS registers 9ab8ba01bSGregory CLEMENT- #clock-cells : should be set to 1. 10ab8ba01bSGregory CLEMENT- clocks : shall be the input parent clock phandle for the clock. 11ab8ba01bSGregory CLEMENT 12ab8ba01bSGregory CLEMENTcpuclk: clock-complex@d0018700 { 13ab8ba01bSGregory CLEMENT #clock-cells = <1>; 14ab8ba01bSGregory CLEMENT compatible = "marvell,armada-xp-cpu-clock"; 15ee2d8ea1SThomas Petazzoni reg = <0xd0018700 0xA0>, <0x1c054 0x10>; 16ab8ba01bSGregory CLEMENT clocks = <&coreclk 1>; 17ab8ba01bSGregory CLEMENT} 18ab8ba01bSGregory CLEMENT 19ab8ba01bSGregory CLEMENTcpu@0 { 20ab8ba01bSGregory CLEMENT compatible = "marvell,sheeva-v7"; 21ab8ba01bSGregory CLEMENT reg = <0>; 22ab8ba01bSGregory CLEMENT clocks = <&cpuclk 0>; 23ab8ba01bSGregory CLEMENT}; 24